CC2430-RTR1-F32Z datasheet(133/234 Pages) TI

133 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 133 of 232

13.8 Random Number Generator

13.8.1 Introduction

The random number generator has the

following features.

•

Generate pseudo-random bytes which

can be read by the CPU or used

directly by the Command Strobe

Processor.

•

Calculate CRC16 of bytes that are

written to RNDH.

•

Seeded by value written to RNDL.

The random number generator is a 16-bit

Linear Feedback Shift Register (LFSR)

with polynomial

(i.e.

CRC16). It uses different levels of

unrolling depending on the operation it

performs. The basic version (no unrolling)

is shown below.

in_bit

Figure 27: Basic structure of the Random Number Generator

The random number generator is turned

off when ADCCON1.RCTRL=”11”.

13.8.2 Random

Number

Generator

Operation

The operation of the random number

generator

controlled

through

combination of the ADCCON1.RCTRL bits

and input signals from other modules. The

current value of the 16-bit shift register in

the LFSR can be read from the RNDH and

RNDL registers.

13.8.2.1 Semi random sequence

generation

The

default

operation

(ADCCON1.RCTRL=”00”) is to clock the

LFSR once (13x unrolling) each time the

Command Strobe Processor reads the

random value. This leads to the availability

of a fresh pseudo-random byte from the

LSB end of the LFSR.

Another way to update the LFSR is to set

ADCCON1.RCTRL=”01”. This will clock

the LFSR once (no unrolling) and the

ADCCON1.RCTRL bits will automatically be

cleared

when

the

operation

has

completed.

13.8.2.2 Seeding

The LFSR can be seeded by writing to the

RNDL register twice. Each time the RNDL

is copied to the 8 MSB and the 8 LSBs are

replaced with the new data byte that was

written to RNDL.

When a true random value is required, the

LFSR can be seeded by writing RNDL with

random values from the ADC in the RF

receive path. To use this seeding method,

the radio must first be powered on by

enabling

the

voltage

regulator

described in section 16.1. The radio

should be placed in infinite TX state, to

avoid possible sync detect in RX state.

The random values from the ADC are read

from the RF registers ADCTSTH and

ADCTSTL (see page 216). The values read

are used as the seed values to be written

to the RNDL register as described above.

13.8.2.3 CRC16

The LFSR can also be used to calculate

the CRC value of a sequence of bytes.

Writing to the RNDH register will trigger a

CRC

calculation.

The new

byte is

processed from the MSB end and an 8x

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