CC2430-RTR1-F64Z datasheet(145/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 145 of 232

13.12 Watchdog Timer

The watchdog timer (WDT) is intended as

a recovery method in situations where the

CPU may be subjected to a software

upset. The WDT shall reset the system

when software fails to clear the WDT

within a selected time interval. The

watchdog can be used in applications that

are subject to electrical noise, power

glitches, electrostatic discharge etc., or

where high reliability is required. If the

watchdog function is not needed in an

application, it is possible to configure the

watchdog timer to be used as an interval

timer that can be used to generate

interrupts at selected time intervals.

The features of the watchdog timer are as

follows:

•

Four selectable timer intervals

•

Watchdog mode

•

Timer mode

•

Interrupt request generation in timer

mode

•

Clock independent from system clock

The WDT is configured as either a

watchdog timer or as a timer for general-

purpose use. The operation of the WDT

module is controlled by the WDCTL

an 15-bit counter clocked by the 32.768

kHz oscillator clock. Note that the contents

of the 15-bit counter is not user-

accessible.

13.12.1 Watchdog mode

The watchdog timer is disabled after a

system reset. To set the WDT in watchdog

mode the WDCTL.MODE bit is set to 0. The

watchdog

timer

counter

starts

incrementing

when

the

enable

bit

WDCTL.EN is set to 1. When the timer is

enabled in watchdog mode it is not

possible to disable the timer. Therefore,

writing a 0 to WDCTL.EN has no effect if a

1 was already written to this bit when

WDCTL.MODE was 0.

The WDT operates with a watchdog timer

clock frequency of 32.768 kHz. This clock

frequency gives time-out periods equal to

1.9 ms, 15.625 ms, 0.25 s and 1 s

corresponding to the count value settings

64, 512, 8192 and 32768 respectively.

If the counter reaches the selected timer

interval

value,

the

watchdog

timer

generates a reset signal for the system. If

a watchdog clear sequence is performed

before the counter reaches the selected

timer interval value, the counter is reset to

0x0000 and continues incrementing its

value. The watchdog clear sequence

consists

writing

0xA

WDCTL.CLR[3:0] followed by writing 0x5

to the same register bits within one half of

a watchdog clock period. If this complete

sequence is not performed, the watchdog

timer generates a reset signal for the

system. Note that as long as a correct

watchdog clear sequence begins within

the selected timer interval, the counter is

reset when the complete sequence has

been received.

When the watchdog timer has been

enabled in watchdog mode, it is not

possible to change the mode by writing to

the WDCTL.MODE bit. The timer interval

value can be changed by writing to the

WDCTL.INT[1:0] bits.

Note that it is recommended that user

software clears the watchdog timer at the

same time as the timer interval value is

changed, in order to avoid an unwanted

watchdog reset.

In watchdog mode, the WDT does not

produce an interrupt request.

13.12.2

Timer mode

To set the WDT in normal timer mode, the

WDCTL.MODE bit is set to 1. When register

bit WDCTL.EN is set to 1, the timer is

started

and

the

counter

starts

incrementing. When the counter reaches

the selected interval value, the timer will

produce an interrupt request.

In timer mode, it is possible to clear the

timer

contents

writing

WDCTL.CLR[0].

When

the

timer

cleared the contents of the counter is set

to 0x0000. Writing a 0 to the enable bit

WDCTL.EN stops the timer and writing 1

restarts the timer from 0x0000.

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