CC2430-RTR1-F64Z datasheet(149/234 Pages) TI

149 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 149 of 232

In SPI master mode, the SSN pin is not

used. When the USART operates as an

SPI master and a slave select signal is

needed by an external SPI slave device,

then a general purpose I/O pin should be

used to implement the slave select signal

function in software.

13.13.4 Baud Rate Generation

An internal baud rate generator sets the

UART baud rate when operating in UART

mode and the SPI master clock frequency

when operating in SPI mode.

The

UxBAUD.BAUD_M[7:0]

and

UxGCR.BAUD_E[4:0] registers define

the baud rate used for UART transfers and

the rate of the serial clock for SPI

transfers. The baud rate is given by the

following equation:

BAUD

Baudrate

BAUD

∗

)

256

(

where F is the system clock frequency, 16

MHz or 32 MHz.

The register values required for standard

baud rates are shown in Table 39 for a

typical system clock set to 32 MHz. The

table also gives the difference in actual

baud rate to standard baud rate value as a

percentage error.

The maximum baud rate for UART mode

is F/16 when BAUD_E is 16 and BAUD_M

is 0, and where F is the system clock

frequency.

The maximum baud rate for SPI mode and

thus SCK frequency, is F/2 when BAUD_E

is 19 and BAUD_M is 0. Setting higher

baud rates than this will give erroneous

results.

Baud rate (bps)

UxBAUD.BAUD_M

UxGCR.BAUD_E

Error (%)

2400

0.14

4800

0.14

9600

0.14

14400

216

0.03

19200

0.14

28800

216

0.03

38400

0.14

57600

216

0.03

76800

0.14

115200

216

0.03

230400

216

0.03

Table 39: Commonly used baud rate settings for 32 MHz system clock

13.13.5 USART flushing

The current operation can be aborted by

setting the UxUCR.FLUSH register bit. This

event will immediately stop the current

operation and clear all data buffers.

13.13.6 USART Interrupts

Each USART has two interrupts. These

are the RX complete interrupt (URXx) and

the TX complete interrupt (UTXx).

The USART interrupt enable bits are found

in the IEN0 and IEN2 registers. The

interrupt flags are located in the TCON and

IRCON2 registers. Refer to section 12.7 on

page 52 for details of these registers. The

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