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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CC2430-RTR1-F64Z датащи(PDF) 142 Page - Texas Instruments |
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CC2430-RTR1-F64Z датащи(HTML) 142 Page - Texas Instruments |
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142 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 142 of 232 13.10.8 Power Management Registers This section describes the Power Management registers. PCON (0x87) – Power Mode Control Bit Name Reset R/W Description 7:2 - 0x00 R/W Not used. 1 - 0 R0 Not used, always read as 0. 0 IDLE 0 R0/W H0 Power mode control. Writing a 1 to this bit forces CC2430 to enter the power mode set by SLEEP.MODE. This bit is always read as 0 SLEEP (0xBE) – Sleep Mode Control Bit Name Reset R/W Description 7 - 0 R0 Unused 6 XOSC_STB 0 R XOSC stable status: 0 – XOSC is not powered up or not yet stable 1 – XOSC is powered up and stable 5 HFRC_STB 0 R HF RCOSC stable status: 0 – HF RCOSC is not powered up or not yet stable 1 – HF RCOSC is powered up and stable 4:3 RST[1:0] XX R Status bit indicating the cause of the last reset. If there are multiple resets, the register will only contain the last event. 00 – Power-on reset 01 – External reset 10 – Watchdog timer reset 2 OSC_PD 1 R/W H0 XOSC and HF RCOSC power down setting. The bit is cleared if the CLKCON.OSC bit is toggled. Also, if there is a calibration in progress and the CPU attempts to set the bit, the bit will be updated at the end of calibration: 0 – Both oscillators powered up 1 – Oscillator not selected by CLKCON.OSC bit powered down 1:0 MODE[1:0] 00 R/W Sleep mode setting: 00 – Power mode 0 01 – Power mode 1 10 – Power mode 2 11 – Power mode 3 |
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