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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CC2430-RTR1-F64Z датащи(PDF) 113 Page - Texas Instruments |
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CC2430-RTR1-F64Z датащи(HTML) 113 Page - Texas Instruments |
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113 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 113 of 232 • T2CAPHPH – Timer 2 Capture/Period High • T2CAPLPL – Timer 2 Capture/Period Low • T2PEROF2 – Timer 2 Overflow Compare/Capture 2 • T2PEROF1 – Timer 2 Overflow Compare/Capture 1 • T2PEROF0 – Timer 2 Overflow Compare/Capture 0 T2CNF (0xC3) – Timer 2 Configuration Bit Name Reset R/W Description 7 CMPIF 0 R/W0 Timer compare interrupt flag. This bit is set to 1 when a timer compare event occurs. Cleared by software only. Writing a 1 to this bit has no effect. 6 PERIF 0 R/W0 Overflow interrupt flag. This bit is set to 1 when a period event occurs. Cleared by software only. Writing a 1 to this bit has no effect. 5 OFCMPIF 0 R/W Overflow compare interrupt flag. This bit is set to 1 when a overflow compare occurs. Cleared by software only. Writing a 1 to this bit has no effect. 4 - 0 R0 Not used. Read as 0 3 CMSEL 0 R/W Timer compare source select. 0 Compare with 16-bit Timer bits [15:8] 1 Compare with 16-bit Timer bits [7:0] 2 - 0 R/W Reserved. Always set to 0 1 SYNC 1 R/W Enable synchronized start and stop. 0 start and stop of timer is immediate 1 start and stop of timer is synchronized with 32.768 kHz edge and new timer values are reloaded. 0 RUN 0 R/W Start timer. Writing this bit shall start or stop the timer. When reading this bit the current state of the timer is returned. 0 stop timer (IDLE state) 1 start timer (RUN state) |
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