CC2430-RTR1-F64Z datasheet(109/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 109 of 232

T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control

Bit

Name

Reset

R/W

Description

Capture select. Timer 1 channel 2 captures on RF interrupt from

RF transceiver or capture input pin

Use normal capture input

CPSEL

R/W

Use RF interrupt from RF transceiver for capture

R/W

Channel 2 interrupt mask. Enables interrupt request when set.

Channel 2 compare mode select. Selects action on output when

timer value equals compare value in

T1CC2

000

Set output on compare

001

Clear output on compare

010

Toggle output on compare

011

Set output on compare-up, clear on 0 (clear on compare-

down in up/down mode)

100

Clear output on compare-up, set on 0 (set on compare-

down in up/down mode)

101

Clear when equal

T1CC0, set when equal T1CC2

110

Set when equal

T1CC0, clear when equal T1CC2

5:3

CMP[2:0]

000

R/W

111

Not used

Mode. Select Timer 1 channel 2 capture or compare mode

Capture mode

MODE

R/W

Compare mode

Channel 2 capture mode select

No capture

Capture on rising edge

Capture on falling edge

1:0

CAP[1:0]

R/W

Capture on all edges

T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High

Bit

Name

Reset

R/W

Description

7:0

T1CC2[15:8]

0x00

R/W

Timer 1 channel 2 capture/compare value, high order byte

T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low

Bit

Name

Reset

R/W

Description

7:0

T1CC2[7:0]

0x00

R/W

Timer 1 channel 2 capture/compare value, low order byte

The TIMIF.OVFIM register bit resides in the TIMIF register, which is described together with

timer 3 and timer 4

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