CC2430-RTR1-F64Z datasheet(115/234 Pages) TI

115 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 115 of 232

T2OF1 (0xA2) – Timer 2 Overflow Count 1

Bit

Name

Reset

R/W

Description

7:0

OF1[7:0]

0x00

R/W

Overflow count. Middle bits T2OF[15:8]. T2OF is incremented by 1

each time the timer overflows i.e. timer counts to a value greater or

equal to period. When reading this register, the value read is the value

latched when T2OF0 was read. Writing to this register when the timer is

in IDLE or RUN states will force the overflow count to be set to the

value written to T2OF2:T2OF1:T2OF0. If the count would otherwise be

incremented by 1 when this register is written then 1 is added to the

value written. The value written will not take effect until T2OF2 is written.

T2OF0 (0xA1) – Timer 2 Overflow Count 0

Bit

Name

Reset

R/W

Description

7:0

OF0[7:0]

0x00

R/W

Overflow count. Low bits T2OF[7:0]. T2OF is incremented by 1 each

time the timer overflows i.e. timer counts to a value greater or equal to

period. Writing to this register when the timer is in IDLE or RUN states

will force the overflow count to be set to the value written to

T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented by

1 when this register is written then 1 is added to the value written. The

value written will not take effect until T2OF2 is written.

T2CAPHPH (0xA5) – Timer 2 Period High Byte

Bit

Name

Reset

R/W

Description

7:0

CAPHPH[7:0]

0xFF

Capture value high/timer period high. Writing this register sets the high

order bits [15:8] of the timer period. Reading this register gives the high

order bits [15:8] of the timer value at the last capture event.

T2CAPLPL (0xA4) – Timer 2 Period Low Byte

Bit

Name

Reset

R/W

Description

7:0

CAPLPL[7:0]

0xFF

R/W

Capture value low/timer period low. Writing this register sets the low

order bits [7:0] of the timer period. Reading this register gives the low

order bits [7:0] of the timer value at the last capture event.

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