CC2430-RTR1-F64 datasheet(157/234 Pages) TI

157 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 157 of 232

13.14 Flash Controller

The

CC2430 contains 32, 64 or 128 KB

flash memory for storage of program code.

The flash memory is programmable from

the user software.

The Flash Controller handles writing and

erasing the embedded flash memory. The

embedded flash memory consists of 64

pages of 2048 bytes each (CC2430-F128).

The flash memory is byte-addressable

from

the

CPU

and

32-bit

word-

programmable.

The flash controller has the following

features:

•

32-bit word programmable

•

Page erase

•

Lock bits for write-protection and code

security

•

Flash erase timing 20 ms

•

Flash write timing (4 bytes) 20 µs

•

Auto

power-down

during

low-

frequency CPU clock read access

13.14.1 Flash Write

Data is written to the flash memory by

using a program command initiated by

writing the Flash Control register, FCTL.

Flash write operations can program any

number of locations in the flash memory at

a time – it is however important to make

sure the pages to be written are erased

first.

A write operation is performed using one

out of two methods;

•

Through DMA transfer

•

Through CPU SFR access.

The DMA transfer method is the preferred

way to write to the flash memory.

A write operation is initiated by writing a 1

to FCTL.WRITE. The address to start

writing at, is given by FADDRH:FADDRL.

During

each

single,

write

operation

FCTL.SWBSY is set high. During a write,

operation the data written to the FWDATA

The

flash

memory

32-bit

word-

programmable, meaning data is written as

32-bit words. Therefore, the actual writing

to flash memory takes place each time

four bytes have been written to FWDATA.

The CPU will not be able to access the

flash, e.g. to read program code, while a

flash write operation is in progress.

Therefore the program code executing the

flash write must be executed from RAM,

meaning that the program code must

reside in the area 0xE000 to 0xFF00 in

CODE memory space.

When a flash write operation is executed

from RAM, the CPU continues to execute

code from the next instruction after the

write to FWDATA, which initiated the flash

write operation.

The FCTL.SWBSY bit must be 0 before

accessing the flash after a flash write,

otherwise an access violation occurs. This

also means that FCTL.SWBSY must be 0

before program execution can continue at

a location in flash memory.

13.14.1.1 DMA Flash Write

When using DMA write operations, the

data to be written into flash is stored in

Data/XDATA memory. A DMA channel is

configured to read the data to be written

from memory and write this data to the

Flash Write Data register, FWDATA, with

the DMA trigger event FLASH enabled.

Thus the Flash Controller will trigger a

DMA transfer when the Flash Write Data

data. The DMA channel should be

configured to perform a block to fixed,

single mode, byte size transfers.

When the DMA channel is armed, starting

a flash write will trigger the first DMA

transfer.

Figure 34 shows an example how a DMA

channel is configured and how a DMA

transfer is initiated to write a block of data

from a location in XDATA to flash memory.

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