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DS0147 датащи(PDF) 87 Page - Microchip Technology |
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DS0147 датащи(HTML) 87 Page - Microchip Technology |
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87 / 128 page ![]() 11. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 12. THGSTATE is based on the condition where the CDR was in lock (to reference or data) for at least 5.2 μs before moving to the high-gain state. At this point, if the receive data is outside the ppm tolerance of the CDR, the CDR will unlock after the time specified by the parameter. 13. The following definitions apply: a. TCDRREF is the transceiver CDR reference clock period in nanoseconds. b. WXCVRFABRX is the parallel interface width of the transceiver receive fabric interface. c. CDRFBDIV is the feedback divider of the transceiver. d. CDRCDRREFDIV is the reference divider of the transceiver CDR. 14. For details on the Enhanced Receiver Management feature, refer to UG0677: PolarFire FPGA Transceiver User Guide. 6.5.6 Transceiver and Receiver Return Loss Characteristics This section describes transmitter and receiver return loss characteristics compliant with OIF-CEI-03.1. Figure 4 • Differential Return Loss Table 92 • Differential Return Loss Unit Value Parameter dB –8 A0 MHz 100 f0 Hz (3/4) * T_Baud f1 Hz T_Baud f2 83 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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