DS0147 datasheet(20/128 Pages) MICROCHIP

20 / 128 page

IOH

2,6

IOL

2,6

VOH

Min (V)

VOL

Max (V)

VDDI

Max (V)

VDDI

Typ (V)

VDDI

Min (V)

I/O Standard

(VDDI – VOH)/3

VOL/34

0.8 × VDDI

0.2 × VDDI

1.418

1.35

1.283

SSTL135II

VDDI – 0.4

0.4

1.575

1.5

1.425

HSTL15I

VDDI – 0.4

0.4

1.575

1.5

1.425

HSTL15II

(VDDI – VOH)/5

VOL/50

0.8 × VDDI

0.2 × VDDI

1.418

1.35

1.283

HSTL135I

(VDDI – VOH)/2

VOL/25

0.8 × VDDI

0.2 × VDDI

1.418

1.35

1.283

HSTL135II

(VDDI – VOH)/5

VOL/50

0.9 × VDDI

0.1 × VDDI

1.26

1.2

1.14

HSTL12I

(VDDI – VOH)/2

VOL/25

0.9 × VDDI

0.1 × VDDI

1.26

1.2

1.14

HSTL12II

(VDDI – VOH)/5

VOL/55

0.9 × VDDI

0.1 × VDDI

1.89

1.8

1.71

HSUL18I

(VDDI – VOH)/2

VOL/25

0.9 × VDDI

0.1 × VDDI

1.89

1.8

1.71

HSUL18II

(VDDI – VOH)/4

VOL/40

0.9 × VDDI

0.1 × VDDI

1.26

1.2

1.14

HSUL12I

(VDDI – VOH)/4

VOL/48

0.5 × VDDI

1.26

1.2

1.14

POD12I

4,5

(VDDI – VOH)/3

VOL/34

0.5 × VDDI

1.26

1.2

1.14

POD12II

4,5

1. Drive strengths per PCI specification V/I curves.

2. Refer to UG0686: PolarFire FPGA User I/O User Guide for details on supported drive strengths.

3. For external stub-series resistance. This resistance is on-die for GPIO.

4. IOL/IOH units for impedance standards in amps (not mA).

5. VOH_MAX based on external pull-up termination (pseudo-open drain).

6. The total DC sink/source current of all IOs within a lane is limited as follows:

a. HSIO lane: 120 mA per 12 IO buffers.

b. GPIO lane: 160 mA per 12 IO buffers.

Note: 3.3 V and 2.5 V are only supported in GPIO banks.

5.3.2

Differential DC Input and Output Levels

The follow tables list the differential DC I/O levels.

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

DC Characteristics

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