UCC28C53_V01 datasheet(19/48 Pages) TI

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RRT

CCT

VREF

RT/CT

GND

8.4 mA

VDDON

VDDOFF

CCT

tON

tOFF

tPERIOD

Figure 8-4. Oscillator Circuit

While the device discharges the timing capacitor, resistor RRT continues attempting to charge CCT. It is the exact

ratio of these two currents, the discharging versus the charging current, which specifies the maximum duty cycle.

During the discharge time of CCT, the device output is always off. This represents an ensured minimum off

time of the switch, commonly referred to as dead-time. To program an accurate maximum duty cycle, use the

information provided in Figure 7-18for maximum duty cycle versus oscillator frequency. Any number of maximum

duty cycles can be programmed for a given frequency by adjusting the values of RRT and CCT. After selecting the

value of RRT, find the oscillator timing capacitance using the curves in Figure 7-1. However, because resistors

are available in more precise increments, typically 1%, and capacitors are only available in 5% accuracy, it might

be more practical to select the closest capacitor value first and then calculate the timing resistor value.

8.3.6 Oscillator Synchronization

Synchronization is best achieved by forcing the timing capacitor voltage above the oscillator internal upper

threshold. A small resistor is placed in series with CCT to GND. This resistor serves as the input for the sync

pulse which raises the CCT voltage above the oscillator internal upper threshold. The PWM is allowed to run

at the frequency set by RRT and CCT until the sync pulse appears. This scheme offers several advantages

including having the local ramp available for slope compensation. The UCCx8C5x oscillator must be set to a

lower frequency than the sync pulse stream, typically 20 percent with a 0.5-V pulse applied across the resistor.

RRT

CCT

VREF

RT/CT

GND

CCT

SYNC

CCT + SYNC

Figure 8-5. Oscillator Synchronization Circuit

8.3.7 Soft-start Timing

The soft-start timing is the technique to gradually power up the converter in a well-controlled fashion by slowly

increasing the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error

amplifier inverting input is low, commanding the error amplifier’s output to go high. The output stage of the

amplifier can source 1 mA typically, which is enough to drive most high impedance compensation networks, but

not enough for driving large loads quickly. Soft-start timing is achieved by charging a fairly large value, >1-µF,

capacitor (CSS) connected to the error amplifier output through a PNP transistor as shown in Figure 8-6

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UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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