UCC28C53_V01 datasheet(16/48 Pages) TI

16 / 48 page

device damage is likely if otherwise. Because of this limitation, the UCCx8C5x devices match the predecessor

bipolar devices, which could survive up to 30 V on the input bias pin. Because no internal clamp is included

in the device, the VDD pin must be protected from external sources which could exceed the 30 V level. If

containing the start-up and bootstrap supply voltage from the auxiliary winding NA below 30 V under all line

and load conditions can not be achieved, use a zener protection diode from VDD to GND. Depending on the

impedance and arrangement of the bootstrap supply, this may require adding a resistor, RVDD, in series with the

auxiliary winding to limit the current into the zener as shown in Figure 8-1. Ensure that over all tolerances and

temperatures, the minimum zener voltage is higher than the highest UVLO upper turn-on threshold. To prevent

noise related problems, filter VDD with a ceramic bypass capacitor to GND. The VDD pin must be decoupled as

close to the GND pin as possible.

RSTART

CVCC

VDD

OUT

GND

CVDDbp

0.1 PF

DBIAS

RCS

RVDD

Input

DZCLAMP

Figure 8-1. VDD Protection

Although quiescent VDD current is only 75 µA, the total supply current is higher, depending on the OUT current.

Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating

frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 1.

IOUT = Qg × fSW

(1)

8.3.1.8 VREF

VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The

5-V reference tolerance is ±1% for the UCCx8C5x family. The high-speed switching logic uses VREF as the

logic power supply. The reference voltage is divided down internally to 2.5 V ±1% and connected to the error

amplifier's noninverting input for accurate output voltage regulation. The reference voltage sets the internal

bias currents and thresholds for functions such as the oscillator upper and lower thresholds along with the

overcurrent limiting threshold. The output short-circuit current is 55 mA (maximum). To avoid device over-heating

and damage, do not pull VREF to ground as a means to terminate switching. For reference stability and to

prevent noise problems with high-speed switching transients, bypass VREF to GND with a ceramic capacitor

close to the IC package. A ceramic capacitor with a minimum value of 0.1 µF is required. Additional VREF

bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition

to the ceramic capacitor.

8.3.2 Undervoltage Lockout

Six sets of UVLO thresholds are available with turn-on and turnoff thresholds of: (14.5 V and 9 V), (8.4 V and

7.6 V), (7 V and 6.6 V), (18.8 V and 15.5 V), (18.8 V and 14.5V) and (16 V and 12.5V), respectively. The first

set is primarily intended for off-line and 48-V distributed power applications, where the wider hysteresis allows

for lower frequency operation and longer soft-starting time of the converter. The second group of UVLO options

is ideal for high frequency DC-DC converters typically running from a 12-VDC input. The third, and newest, set

has been added to address battery powered and portable applications. Table 8-2 shows the maximum duty cycle

and UVLO thresholds by device.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

www.ti.com

Submit Document Feedback

Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

UCC28C53 датащи(PDF) 16 Page - Texas Instruments

UCC28C53 датащи(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL