MMPF0100 datasheet(16/137 Pages) NXP

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NXP Semiconductors

PF0100

GENERAL DESCRIPTION

5.2

Functional block diagram

Figure 5. Functional block diagram

5.3

Functional description

5.3.1

Power generation

The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one

switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices.

The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher

current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further,

SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can

also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and

to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for

the processor cores and/or other circuitry.

Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input

supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR

voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The

VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be

powered from VIN, or from a coin cell.

5.3.2

Control logic

The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including

interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by

configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.

The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply

of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell

is included as well.

Logic and control

Switching regulators

SW1A/B/C

(0.3 V to 1.875 V)

Configurable 4.5 A or

2.5 A+2.0 A

Linear regulators

SW2

(0.4 V to 3.3 V, 2.0 A)

SW3A/B

(0.4 V to 3.3 V)

Configurable 2.5 A

or 1.25 A+1.25 A

SW4

(0.4 V to 3.3 V, 1.0 A)

Boost Regulator

(5.0 V to 5.15 V, 600 mA)

USB OTG Supply

VGEN1

(0.8 V to 1.55 V, 100 mA)

VGEN2

(0.8 V to 1.55 V, 250 mA)

VGEN3

(1.8 V to 3.3 V, 100 mA)

VGEN4

(1.8 V to 3.3 V, 350 mA)

VGEN5

(1.8 V to 3.3 V, 100 mA)

VGEN6

(1.8 V to 3.3 V, 200 mA)

Bias & references

Parallel MCU interface

Regulator control

VSNVS

(1.0 V to 3.0 V, 400

μA)

RTC supply with coin cell

charger

MMPF0100 functional internal block diagram

I2C communication and registers

Power generation

Fault detection and protection

DDR voltage reference

Current limit

Short-circuit

Internal core voltage reference

Thermal

OTP startup configuration

Sequence and

timing

OTP prototyping

(Try before buy)

Voltage

Phasing and

frequency selection

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