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WM8522 датащи(PDF) 32 Page - Wolfson Microelectronics plc |
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WM8522 датащи(HTML) 32 Page - Wolfson Microelectronics plc |
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32 / 39 page ![]() WM8522 Pre-Production w PP Rev 3.1 May 2006 32 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION In left/right/I 2S Modes: LRCLK Polarity (normal) 0 : Normal LRCLK polarity 1: Inverted LRCLK polarity 2 LRP 0 In DSP Mode: 0 : DSP mode A 1: DSP mode B 3 BCP 0 BCLK Polarity (DSP Modes): 0: Normal BCLK polarity 1: Inverted BCLK polarity 5:4 IWL[5:4] 00 Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Bit DAC Phase 0 DAC1L/R 1 = invert 1 DAC2L/R 1 = invert 8:6 PHASE [8:6] 000 2 DAC3L/R 1 = invert 7:0 LDA2[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 16 R4 (04h) Digital Attenuation DACL2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. 7:0 RDA2[7:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 16 R5 (05h) Digital Attenuation DACR2 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. 7:0 LDA3[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 16 R6 (06h) Digital Attenuation DACL3 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. 7:0 RDA3[7:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 16 R7 (07h) Digital Attenuation DACR3 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. 7:0 MASTDA [7:0] 11111111 (0dB) Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 16 R8 (08h) Master Digital Attenuation (all channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. 0 ZCD 0 DAC Digital Volume Zero Cross Enable: 0: Zero cross detect enabled 1: Zero cross detect disabled 2:1 DZFM[1:0] 00 Zero flag/mute decode. See Table 11, Table 12 and Table 13 for details. R9 (09h) DAC Mute 5:3 DMUTE [2:0] 000 DAC Soft Mute Select. See Table 10 for details. |
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