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WM8522 датащи(PDF) 31 Page - Wolfson Microelectronics plc |
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WM8522 датащи(HTML) 31 Page - Wolfson Microelectronics plc |
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31 / 39 page ![]() Pre-Production WM8522 w PP Rev 3.1 May 2006 31 REGISTER MAP DESCRIPTION REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 LDA1[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 16 R0 (00h) Digital Attenuation DACL1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels 7:0 RDA1[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 16. R1 (01h) Digital Attenuation DACR1 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. 0 MUTEALL 0 Soft Mute Select: 0 : Normal operation 1: Soft mute all channels 1 DEEMPALL 0 DEEMPH Select: 0 : Normal operation 1: De-emphasis all channels 2 PDWN 0 Power Down all DAC’s Select: 0: All DACs enabled 1: All DACs disabled 3 ATC 0 Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations 4 IZD 0 IZD Enable 0 : Disable infinite zero mute 1: Enable infinite zero mute PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 R2 (02h) DAC DEEMPH 8:5 PL[3:0] 1001 1111 (L+R)/2 (L+R)/2 R3 (03h) DAC Phase 1:0 FMT[1:0] 00 Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I 2S mode 11: DSP modes A or B |
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