MCP6V51-ESLASHMS datasheet(7/50 Pages) MICROCHIP

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2018-2022 Microchip Technology Inc. and its subsidiaries

DS20006136B-page 7

MCP6V51/2/4

1.3

Timing Diagrams

The Timing Diagrams provide a depiction of the

Amplifier Step Response specifications listed under the

AC Electrical Specifications table.

FIGURE 1-1:

Amplifier Start-up.

FIGURE 1-2:

Offset Correction Settling

Time.

FIGURE 1-3:

Output Overdrive Recovery.

1.4

Test Circuits

The circuits used for most DC and AC tests are shown in

Figure 1-4 and Figure 1-5. Lay the bypass capacitors out

as discussed in

Section 4.3.10 “Supply Bypassing

and Filtering”. RN is equal to the parallel combination of

RF and RG to minimize bias current effects.

FIGURE 1-4:

AC and DC Test Circuit for

Most Noninverting Gain Conditions.

FIGURE 1-5:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic

behavior (i.e., tSTR, tSTL and tODR). The potentiometer

balances the resistor network (VOUT should equal VREF

at DC). The op amp’s Common-Mode Input Voltage is

VCM = VIN/3. The error at the input (VERR) appears at

VOUT with a noise gain of approximately 10 V/V.

FIGURE 1-6:

Test Circuit for Dynamic

Input Behavior.

VDD

VOUT

1.01(VDD/3)

0.99(VDD/3)

tSTR

VDD

2.3V

VIN

VOS

VOS + 100 µV

VOS – 100 µV

tSTL

VIN

VOUT

VDD

VSS

tODR

VDD/2

VDD

VOUT

VIN

VDD/3

1 µF

100 nF

RISO

MCP6V5X

–

VDD

VOUT

VDD/3

VIN

1 µF

100 nF

RISO

MCP6V5X

VDD

VOUT

1 µF

RISO

1.1 kΩ

249Ω

1.1 kΩ

500Ω

VIN

VREF = VDD/3

0.1%

25 Turn

10 kΩ

0.1%

0 Ω

100 pF

open

100 nF

MCP6V5X

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