25CSM04-ISLASHMF datasheet(9/55 Pages) MICROCHIP

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DS20005817D-page 9

25CSM04

1.2

Device Default State

1.2.1

POWER-UP DEFAULT STATE

The 25CSM04 default state upon power-up consists of:

• Standby mode (CS = HIGH)

• A high-to-low level transition on CS is required to

enter the active state

• Write Enable Latch (WEL) bit in the STATUS

• Error Correction State Latch (ECS) bit in the

STATUS register = 0

• Partition Register Write Enable Latch (PREL) bit

in the STATUS register = 0

• Ready/Busy (RDY/BUSY) bit in the STATUS

accept a new instruction

1.2.2

DEVICE FACTORY DEFAULT

CONDITION

The 25CSM04 is shipped to the customer with the

EEPROM array set to an all FFh data pattern (logic ‘1’

state).

The Security register contains a preprogrammed,

128-bit serial number in the lower 16 bytes. The

user-programmable portion (lockable ID page) is

unlocked and set to logic ‘1’ resulting in 256 bytes of

FFh data. In the various device registers, the following

nonvolatile bits are set:

• Write Protection Enable (WPEN) bit in the

STATUS register is set to logic ‘0’ allowing writing

to the STATUS register. (See Table 1-5).

• Block Write-Protect (BP[1:0] bits in the STATUS

set when in Legacy mode. (See Table 1-5).

• Write Protection Mode (WPM) bit in the STATUS

set for Legacy Write Protection mode. (See

Table 1-6).

• Freeze Memory Protection Configuration (FMPC)

bit in the STATUS register is set to logic ‘0’,

indicating the Memory Partition Registers (MPRs)

and the Write Protection Mode (WPM) bit are not

locked and can be changed. (See Table 1-6).

• Protect Address Boundary Protection (PABP) bit

in the STATUS register is set to logic ‘0’, indicat-

ing the partition endpoint address value in each

MPR can be modified. (See Table 1-6).

• Memory Partition Registers (MPR0-MPR7) are

set to 00h, indicating that the entire 4 Mbit

memory can be written. (See Table 1-7).

TABLE 1-5:

STATUS REGISTER BITS – BYTE 0 (FACTORY DEFAULT)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN

Reserved

BP1

BP0

WEL(1)

RDY/BUSY(1)

000

Note 1: These bits are volatile and reset to this value upon power-up.

TABLE 1-6:

STATUS REGISTER BITS – BYTE 1 (FACTORY DEFAULT)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPM

ECS(1)

FMPC

PREL(1)

PABP

Reserved

RDY/BUSY(1)

000

Note 1: These bits are volatile and reset to this value upon power-up.

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