25CSM04-ISLASHMF datasheet(20/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 20

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6.1.1

WRITE-PROTECT ENABLE BIT

The Write-Protect Enable (WPEN) bit in the STATUS

the WP pin to inhibit writing to the various registers

within the device.

The device is hardware write-protected when both the

WP pin is low and the WPEN bit has been set to a

logic ‘1’. The affected registers depend on the write

protection mode selected.

The write protection mode is determined by the WPM

bit in the STATUS register (bit 7, byte 1). Hardware

write protection is disabled when either the WP pin is

deasserted (high) or the WPEN bit is a logic ‘0’.

Table 6-1 describes which registers will be protected

from being modified. The WP pin must be asserted

(low) to enable any protection capabilities.

STATUS REGISTER (BYTE 1)

R/W-1

R-0

U-0

R-0

WPM

ECS

FMPC

PREL

PABP

—

RDY/BSY

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WPM: Write Protection Mode bit(1)

1 = Enhanced Write Protection mode selected

0 = Legacy Write Protection mode selected

bit 6

ECS: Error Correction State Latch bit

1 = The previously executed read sequence did require the Error Correction Code (ECC)

0 = The previous executed read sequence did not require the Error Correction Code (ECC)

bit 5

FMPC: Freeze Memory Protection Configuration bit(2)

1 = Memory Partition registers and write protection mode are permanently frozen and cannot be

modified

0 = Memory Partition registers and write protection mode are not frozen and are modifiable

bit 4

PREL: Partition Register Write Enable Latch bit

1 = PRWE has been executed and WMPR, FRZR and PPAB instructions are enabled

0 = WMPR, FRZR and PPAB instructions are disabled

bit 3

PABP: Partition Address Boundary Protection bit

1 = Partition Address Endpoints set in Memory Partition registers cannot be modified

0 = Partition Address Endpoints set in Memory Partition registers are modifiable

bit 2-1

Unimplemented: Read as ‘0’

bit 0

RDY/BSY: Ready/Busy Status Latch bit

1 = Device is busy with an internal write cycle

0 = Device is ready for a new sequence

Note 1: If the FMPC bit is set to a logic ‘1’, the WPM bit is read-only.

2: Once the FMPC bit has been set, it cannot be cleared.

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