CC2652PSIP datasheet(39/72 Pages) TI

39 / 72 page

9.3 Radio (RF Core)

The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor

that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and

assembles the information bits in a given packet structure. The RF core offers a high level, command-based

API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not

programmable by customers and is interfaced through the TI-provided RF driver that is included with the

SimpleLink Software Development Kit (SDK).

The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the

main CPU, which reduces power and leaves more resources for the user application. Several signals are also

available to control external circuitry such as RF switches or range extenders autonomously.

Multiprotocol solutions are enabled through time-sliced access of the radio, handled transparently for the

application through the TI-provided RF driver and dual-mode manager.

The various physical layer radio formats are partly built as a software defined radio where the radio behavior is

either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with

the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards

even with over-the-air (OTA) updates while still using the same silicon.

9.3.1 Bluetooth 5.2 Low Energy

The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-sped 2-Mbps physical layer

and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or

through a high-level Bluetooth API. The Bluetooth 5.2 PHY and part of the controller are in radio and system

ROM, providing significant savings in memory usage and more space available for applications.

The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times

the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers

significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.

Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application

needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible

at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not

previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster

responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates.

9.3.2 802.15.4 (Thread, Zigbee, 6LoWPAN)

Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer

(2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN protocols. The

802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free protocol stacks for Thread

and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution.

9.4 Memory

The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is

in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration

section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is

done through the ccfg.c source file that is included in all TI provided examples.

The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both

storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by

default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in

memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always

initialized to zeroes upon code execution from boot.

To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way

nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.

The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area

(CCFG).

www.ti.com

CC2652PSIP

SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022

Submit Document Feedback

Product Folder Links: CC2652PSIP

CC2652PSIP датащи(PDF) 39 Page - Texas Instruments

CC2652PSIP датащи(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL