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Die Size (Unsawn)

2400 x 1650

95 x 65

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC154

Dual 1-of-16 Decoder / Demultiplexer in bare die form



Output Drive Capability: 10 LSTTL Loads



Low Input Current: 1µA



Outputs directly interface CMOS, NMOS and TTL



Operating Voltage Range: 2V to 6V



CMOS High Noise Immunity



Function compatible with 54LS154



Full Military Temperature Range.

Rev 1.0

30/05/22

Features:

Ordering Information

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection



“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT



“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (100 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 350µm(14 Mils) – On request



Assembled into Ceramic Package – On request

The 54HC154 is fabricated using a 2.5µm 5V CMOS

process and has the same high speed performance of

LSTTL combined with CMOS low power consumption. The

device consists of x4 active-high binary address inputs, x16

active-low outputs & x2 active-low chip-selects. The x2

active-low chip-selects can be used to strobe & eliminate

normal decoding ‘glitches’ on the outputs, or can be used to

expand the decoder. Both chip-selects must be low to

enable the outputs. The demultiplexing function is executed

by use of one chip-select input as multiplexed data input.

When the other chip-select input is low, the addressed

output will follow the state of the applied data.

Description

Die Dimensions in µm (mils)

2400 (95)