High Speed CMOS Logic – 54HC154

Rev 1.0

30/05/22

Pad Description

ADDRESS INPUTS

A0, A1, A2, A3

(Pads 23, 22, 21, 20)

These inputs, when the 1-of-16 decoder is enabled, determine which of its sixteen active-low outputs is selected.

CONTROL INPUTS

CS1, CS2

(Pads 18, 19)

Active-low chip-select inputs. With a low level on both inputs, the outputs of the decoder follow the Address inputs. A high level on

either input forces all outputs to a high level.

OUTPUTS

Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15

(Pads 1-11, Pads 13-17)

Active-low outputs. These outputs assume a low level when addressed and both chip-select inputs are active. These outputs remain

high when not addressed or when a chip-select input is high.

Truth Table

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