LTM2887 datasheet(24/30 Pages) AD

24 / 30 page

LTM2810

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

RF, Magnetic Field Immunity

TheisolatorµModuletechnologyusedwithintheLTM2810

hasbeenindependentlyevaluated,andsuccessfullypassed

the RF and magnetic field immunity testing requirements

per European Standard EN 55024, in accordance with the

following test standards:

EN 61000-4-3 Radiated, radio-frequency, electromag-

netic field immunity

EN 61000-4-8 Powerfrequencymagneticfieldimmunity

EN 61000-4-9 Pulsed magnetic field immunity

Tests were performed using an unshielded test card de-

signed per the data sheet PCB layout recommendations.

Specific limits per test are detailed in Table 4.

Table 4. EMC Immunity Tests

TEST

FREQUENCY

FIELD STRENGTH

EN 61000-4-3 Annex D

80MHz to 1GHz

10V/m

1.4MHz to 2GHz

3V/m

2GHz to 2.7GHz

1V/m

EN 61000-4-8 Level 4

50Hz and 60Hz

30A/m

EN 61000-4-8 Level 5

60Hz

100A/m*

EN 61000-4-9 Level 5

Pulse

1000A/m

* Non IEC method.

PCB Layout

The high integration of the LTM2810 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics and EMI performance, some layout con-

siderations are necessary.

• Input and output supply decoupling is not required,

since these components are integrated within the pack-

age. An additional bulk capacitor with a value of 6.8µF

to 22µF with 1Ω to 3Ω of ESR is recommended. The

high ESR of this capacitor reduces board resonances

and minimizes voltage spikes caused by hot plugging

of the supply voltage. For EMI sensitive applications, an

additional low ESL ceramic capacitor of 1µF to 4.7µF,

placed as close to the power and ground terminals as

possible, is recommended. Alternatively, a number of

smaller value parallel capacitors may be used to reduce

ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner col-

umns of pads. This area must remain open to withstand

the rated isolation voltage.

• The use of solid ground planes for GND and GND2

is recommended for non-EMI critical applications to

optimize signal fidelity, and minimize RF emissions

due to uncoupled PCB trace conduction. The drawback

of using ground planes where EMI is of concern, is

the creation of a dipole antenna structure which can

radiate differential voltages formed between GND and

GND2. If ground planes are used, it is recommended

to minimize their area, and use contiguous planes as

any openings or splits can exacerbate RF emissions.

• For large ground planes a small capacitance (≤ 330pF)

from GND to GND2, either discrete or embedded within

the substrate, provides a low impedance current return

path for the module parasitic capacitance, minimizing

anyhighfrequencydifferentialvoltagesandsubstantially

reducing radiated emissions. Discrete capacitance will

notbeaseffectiveduetoparasiticESL.Inaddition,volt-

age rating, leakage, and clearance must be considered

for component selection. Embedding the capacitance

withinthePCBsubstrateprovidesanearidealcapacitor

and eliminates component selection issues; however,

the PCB must be 4 layers. Care must be exercised in

applying either technique to ensure the voltage rating

of the barrier is not compromised.

• In applications without an embedded PCB substrate

capacitance, a slot may be added between the logic

side and isolated side device pins. The slot extends the

creepage path between terminals on the PCB side, and

may reduce leakage caused by PCB contamination. The

slot should be placed in the middle of the device and

extend beyond the package perimeter.

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