LTM2887 datasheet(22/30 Pages) AD

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LTM2810

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

Inter-IC Communication (I2C) Bus

The LTM2810-I provides an isolated I2C compatible inter-

face supporting master mode only, with a unidirectional

clock (SCL), and bidirectional data (SDA). The maximum

data rate is 400kHz which supports fast-mode I2C. Timing

is detailed in Figure 10. The data rate is limited by the slave

acknowledge setup time (tSU;ACK), consisting of the I2C

standardminimumsetuptime(tSU;DAT)of100ns,maximum

clock propagation delay of 225ns, glitch filter and isolated

data delay of 500ns maximum, and the combined isolated

and logic data fall time of 300ns at maximum bus load-

ing. The total setup time reduces the I2C data hold time

(tHD;DAT) to a maximum of 175ns, guaranteeing sufficient

data setup time (tSU;ACK).

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements

for bus capacitances greater than 200pF in fast mode and

greater than 400pF in standard mode.

Additional proprietary circuitry monitors the slew rate on

the SDA and SDA2 signals to manage directional control

across the isolation barrier. Slew rates on both pins must

be greater than 1V/μs for proper operation.

Figure 10. I2C Timing Diagram

Figure 11. Isolated SDA2 Pin Schematic

2810 F10

tPROP

tSU;DAT

SDA

SDA2

SCL

SCL2

tHD;DAT

tSU;ACK

STOP

START

SLAVE ACK

2810 F11

SDA2

1.8mA

GLITCH

FILTER

TO LOGIC SIDE

FROM LOGIC SIDE

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