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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F510-I/LSQTP датащи(PDF) 19 Page - Microchip Technology |
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PIC12F510-I/LSQTP датащи(HTML) 19 Page - Microchip Technology |
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19 / 114 page  © 2006 Microchip Technology Inc. Preliminary DS41268B-page 17 PIC12F510/16F506 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (see Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY – PIC12F510 TABLE 4-2: SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset N/A TRIS I/O Control Registers (TRISGPIO) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 1111 1111 03h STATUS GPWUF CWUF PA0 TO PD ZDC C 0001 1xxx 04h FSR Indirect Data Memory Address Pointer 100x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 07h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 08h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 09h ADRES ADC Conversion Result xxxx xxxx Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset N/A TRIS I/O Control Registers (TRISB, TRISC) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 1111 1111 03h STATUS RBWUF CWUF PA0 TO PD ZDC C 0001 1xxx 04h FSR Indirect Data Memory Address Pointer 100x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 08h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 09h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 0Ah ADRES ADC Conversion Result xxxx xxxx 0Bh CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 0Ch VRCON VREN VROE VRR —VR3 VR2 VR1 VR0 001- 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. |
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