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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F510-I/LSQTP датащи(PDF) 58 Page - Microchip Technology |
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PIC12F510-I/LSQTP датащи(HTML) 58 Page - Microchip Technology |
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58 / 114 page  PIC12F510/16F506 DS41268B-page 56 Preliminary © 2006 Microchip Technology Inc. REGISTER 10-1: CONFIGURATION WORD – PIC12F510 — — — — — — IOSCFS MCLRE CP WDTE FOSC1 FOSC0 bit 11 bit 0 bit 11-6: Unimplemented: Read as ‘1’ bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC speed 0 = 4 MHz INTOSC speed bit 4: MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD bit 3: CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator with 18 ms DRT 01 = XT oscillator with 18 ms DRT 10 = INTOSC with 1.125 ms DRT(1), (2) 11 = EXTRC with 1.125 ms DRT(1), (2) Note 1: Refer to the “PIC12F510 Memory Programming Specification”, DS41257 to determine how to access the Configuration Word. 2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown |
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