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Product data sheet

Rev. 01 — 14 February 2006

10 of 30

Philips Semiconductors

PCA9506

7.3.1 IP0 to IP4 - Input Port registers

These registers are read-only. They reflect the incoming logic levels of the port pins

regardless of whether the pin is defined as an input or an output by the I/O Configuration

register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted

incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes

to these registers have no effect.

The Polarity Inversion register can invert the logic states of the port pins. The polarity of

the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The

polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to

logic 0.

Mask Interrupt registers

20

100000

MSK0

read/write

Mask Interrupt register bank 0

21

100001

MSK1

read/write

Mask Interrupt register bank 1

22

100010

MSK2

read/write

Mask Interrupt register bank 2

23

100011

MSK3

read/write

Mask Interrupt register bank 3

24

100100

MSK4

read/write

Mask Interrupt register bank 4

25

100101-

-

reserved for future use

26

100110-

-

reserved for future use

27

100111-

-

reserved for future use

Table 3:

Register #

(hex)

D5

D4

D3

D2

D1

D0

Symbol

Access

Description

Table 4:

IP0 to IP4 - Input Port registers (address 00h to 04h) bit description

Legend: * default value ‘X’ determined by the externally applied logic level.

Address

Register

Bit

Symbol

Access

Value

Description

00h

IP0

7 to 0

I0[7:0]

R

XXXX XXXX*

Input Port register bank 0

01h

IP1

7 to 0

I1[7:0]

R

XXXX XXXX*

Input Port register bank 1

02h

IP2

7 to 0

I2[7:0]

R

XXXX XXXX*

Input Port register bank 2

03h

IP3

7 to 0

I3[7:0]

R

XXXX XXXX*

Input Port register bank 3

04h

IP4

7 to 0

I4[7:0]

R

XXXX XXXX*

Input Port register bank 4