TUSB1104 datasheet(4/55 Pages) TI

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Table 4-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

SSTX2p

Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit

port through an external 220 nF AC-coupling capacitor.

SSTX2n

Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit

port through an external 220 nF AC-coupling capacitor.

No internal connection.

SSRX2p

Differential positive output for USB port 2. Should be connected to USB 3.2 Host receiver

port through an external 220 nF AC-coupling capacitor.

SSRX2n

Differential negative output for USB port 2. Should be connected to USB 3.2 Host receiver

port through an external 220 nF AC-coupling capacitor.

VIO_SEL

4-level I

(PU/PD)

Selects the input thresholds for I2C (SDA and SCL).

"0": I2C 3.3 V

"R": I2C 1.8 V

"F": I2C 3.3 V.

"1": I2C 1.8 V.

SSTX1n

Differential negative input for USB port 1. Should be connected to USB 3.2 Host transmit

port through an external 220 nF AC-coupling capacitor.

SSTX1p

Differential positive input for USB port 1. Should be connected to USB 3.2 Host transmit

port through an external 220 nF AC-coupling capacitor.

MODE

4-level I

(PU/PD)

This pin selects whether device is in I2C mode or pin-strap mode. Refer to Table 7-5 for

details.

SSRX1n

Differential negative output for USB port 1. Should be connected to USB 3.2 Host receiver

port through an external 220 nF AC-coupling capacitor.

SSRX1p

Differential positive output for USB port 1. Should be connected to USB 3.2 Host receiver

port through an external 220 nF AC-coupling capacitor.

VCC

3.3 V supply

FLIP/SCL

In I2C mode, this pin functions as I2C clock. In pin-strap

mode, this pin controls which lane is the config lane (Refer to Table 7-4).

AEQENZ/SDA

I/O

In I2C mode, this pin functions as I2C data. In pin-strap mode, this pin controls whether or

not AEQ is enabled.

0: AEQ enabled

1: AEQ disabled

AEQCFG

4-level I

(PU/PD)

In pin-strap mode, this pin controls the FULLAEQ_UPPER_EQ limit. In I2C mode, this

function is controlled by the FULLAEQ_UPPER_EQ register.

"0": FULLAEQ_UPPER_EQ = Ah

"R": FULLAEQ_UPPER_EQ = Fh

"F": FULLAEQ_UPPER_EQ = 8h

"1": FULLAEQ_UPPER_EQ = Ch

No internal connection

(PU)

When low, the differential receiver's termination will be disabled and differential drivers will

be disabled. On rising edge of EN, device will sample four-level inputs and function based

on the sampled state of the pins. This pin has a internal 500k pull-up to VCC. Please note

this pin will also reset internal configuration registers.

TEST1

TI Test1. Under normal operations this pin shall be connected directly or pulled up to VCC.

VCC

3.3 V supply

CEQ1

4-level I

(PU/PD)

In pin-strap mode, this pin along with CEQ0 selects the receiver EQ for CRX1 and/or

CRX2 (Refer to Table 7-2).

CRX1p

Differential positive input for USB port 1. Should be connected to RX1p pin of USB

connector. Connection can be DC-coupled to USB connector. Optionally, connection can

be through an external 330 nF AC-coupling capacitor.

CRX1n

Differential negative input for USB port 1. Should be connected to RX1n pin of USB

connector. Connection can be DC-coupled to USB connector. Optionally, connection can

be through an external 330 nF AC-coupling capacitor.

TUSB1104

SLLSFL1 – APRIL 2022

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