This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible

problem with this technique, however, is that a voltage divider is created with the added series resistor and any

resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output

that reduces the output swing.

C

load

+

±

V

in

V

out

+V

s

R

iso

-V

s

Figure 8-1. Improving Capacitive Load Drive

8.3.5 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated

state to a linear state. The output devices of the operational amplifier enter a saturation region when the

output voltage exceeds the rated operating voltage, because of the high input voltage or high gain. After one

of the output devices enters the saturation region, the output stage requires additional time to return to the

linear operating state which is referred to as overload recovery time. After the output stage returns to its linear

operating state, the amplifier begins to slew at the specified slew rate. Therefore, the propagation delay (in case

of an overload condition) is the sum of the overload recovery time and the slew time.

8.3.6 Input and ESD Protection

The OPAx310 family incorporates internal ESD protection circuits on all pins. For inputs, this protection primarily

consists of fail safe ESD input structures which feature no current-steering diodes connected between the input

and positive power-supply pin. This is very useful during power sequencing scenarios where input signal can be

present before the positive power supply rail. A fail safe input ESD structure prevents any short between inputs

and positive power supply.

8.3.7 Shutdown Function

The OPAx310 S devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode.

In this mode, the op amp typically consumes about 500 nA at room temperature. The SHDN pins are active low,

meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 500 mV (typical) and does not change with respect to the supply voltage. Hysteresis has

been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown

behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage

between V– and (V–) + 0.2 V. A valid logic high is defined as a voltage between (V–) + 1 V and V+. To enable

the amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins must

be driven to a valid logic low. We highly recommend that the shutdown pin be connected to a valid high or a low

voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level

will damage the device.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad

op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature can be

used to greatly reduce the average current and extend battery life. The enable and disable time is targeted to be

under 1 µs for full shutdown of all channels. When disabled, the output assumes a high-impedance state. This

architecture allows the OPAx310S to be operated as a gated amplifier (or to have the device output multiplexed

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10 kΩ load to

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