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7.7 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Quiescent

current per

amplifier

VS = 5.5 V, IO = 0 A

165

200

µA

TA = –40°C to 125°C

215

Power-on time

At TA = 25°C, VS = 5.5 V, VS ramp rate > 0.3 V/µs

125

μs

SHUTDOWN

IQSD

Shutdown

current per

amplifier

All amplifiers disabled, SHDN = V–

0.5

µA

IQSD

Shutdown

current per

amplifier

All amplifiers disabled, SHDN = V–, TA = –40℃ to 125℃

1.5

µA

ZSHDN

Output

impedance

during shutdown

Amplifier disabled

43 || 11.5

GΩ || pF

VIH

Logic high

threshold

voltage

(amplifier

enabled)

(V–) + 1.2

VIL

Logic low

threshold

voltage

(amplifier

disabled)

(V–) + 0.4

tON

Amplifier enable

time (full

shutdown) (5) (6)

G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–

µs

Amplifier enable

time (partial

shutdown) (5) (6)

G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–

tOFF

Amplifier disable

time (5)

G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V–

µs

SHDN pin input

bias current (per

pin)

(V+) ≥ SHDN ≥ (V–) + 1 V

(V–) ≤ SHDN ≤ (V–) + 0.2 V

100

(1)

Max data is specified based on characterization results.

(2)

Typical input current noise data is specified based on design simulation results

(3)

Third-order filter; bandwidth = 80 kHz at –3 dB.

(4)

Short circuit current specified here is average of sourcing and sinking short circuit currents

(5)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(6)

Full shutdown refers to the dual OPA2310S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad OPA4310S

having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode,

the internal biasing circuitry remains operational and the enable time is shorter.

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