AD3552R datasheet(24/68 Pages) AD

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Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 24 of 68

PRODUCT DESCRIPTION

The AD3552R is a 16-bit, 33 MUPS dual DAC with programmable

output ranges and a 2.5 V internal reference.

The AD3552R has the following two update modes:

►

Fast Mode: data written in this mode is 16 bits long, resulting in a

single-channel update rate of 33 MUPS. The DNL specification is

valid for the reduced temperature range defined in Table 2. The

data for this mode is written in the registers ending in _16B.

►

Precision Mode: data written in this mode is 24 bits long, result-

ing in a single-channel update rate of 22 MUPS. The DNL

specification is guaranteed over the full operating temperature

range. The data for this mode is written in the registers ending in

_24B.

The AD3552R offers a versatile SPI interface capable of operating

in classic, dual, and quad SPI modes with single or double data

rate. The AD3552R features multiple error checkers, both in the

analog and digital domains to guarantee a safe operation.

DAC ARCHITECTURE

The AD3552R uses a current steering DAC architecture with a VREF

voltage of 2.5 V. The DAC current is converted to voltage by means

of an external TIA.

Figure 67 shows the internal block diagram.

Figure 67. DAC Channel Architecture Block Diagram

The TIA feedback loop is closed by hardwiring the VOUT pin to any

of the available RFBx_y pins. The RFBx_y value sets the maximum

voltage span that can be achieved. These voltage spans can be

decreased using the gain scaling registers and repositioned within

the supply rails of the TIA using the offset registers.

PREDEFINED OUTPUT VOLTAGE SPANS

The AD3552R comes with five predefined voltage spans that are

selected using the CH0_CH1_OUTPUT_RANGE register. The se-

lected span must be in accordance with the feedback resistor

being used, as shown in Table 8. The CHx_GAIN_SCALING_P,

CHx_GAIN_SCALING_N, and CHx_OFFSET parameters do not

have to be set because their preset values are provided only as

starting points for the user to create custom range values. Setting a

voltage span that is not achievable with the current RFBx_y resistor

results in an incorrect voltage value.

There is approximately a 3% overrange equally split on each end

of the span to ensure that the nominal range is covered in any

condition.

If the predefined voltage spans do not fit the intended application,

custom spans can be defined using the gain scaling and offset

registers as described in the Custom Output Voltage Span section.

Table 8. Predefined Output Span Ranges and Corresponding Feedback Resistor

RFBx_y

CH0_CH1_OUTPUT_RANGE

Output Span

CHx_GAIN_SCALING_P CHx_GAIN_SCALING_N CHx_OFFSET

RFB1_y

0x000

2.5 V

−24

0x001

5 V

RFB2_y

0x010

10 V

248

0x011

±5 V

−248

RFB4_y

0x100

±10 V

−123

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