AD3552R datasheet(11/68 Pages) AD

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Data Sheet

AD3552R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 68

Figure 13. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

DVDD

Digital Core Power Supply. 1.8 V ± 5%.

VLOGIC

Digital Interface Power Supply. 1.2 V to 1.8 V.

Chip Select, Active Low Logic Input. This is the frame synchronization signal for the input data.

SCLK

Serial Clock Input.

SDI/SDIO0

DI/O

Serial Data Input in Classic SPI Mode.

Serial Bidirectional Input/Output Bit 0 in Dual or Quad SPI Modes.

SDO/SDIO1

DI/O

Serial Data Output in Classic SPI Mode.

Serial Bidirectional Input/Output Bit 1 in Dual or Quad SPI Modes.

SDIO2

DI/O

Serial Bidirectional Input/Output Bit 2 in Quad SPI Mode. Pull down if not used.

SDIO3

DI/O

Serial Bidirectional Input/Output Bit 3 in Quad SPI Mode. Pull down if not used.

LDAC

Load DAC, Active Low Logic Input. LDAC can be operated in synchronous mode or asynchronous mode. Pulsing this pin low

causes the DAC register to be updated if the input register has new data. If this pin is tied permanently low, the DAC is

automatically updated when new data is written to the input register.

RESET

Asynchronous Reset Input. Active low logic input. When RESET is low, all registers are reset to their default values and the activity

on the digital interface is ignored. The AD3552R incorporates a power-on reset (POR) circuit. If this pin is not used it must be tied to

VLOGIC.

ALERT

Alert Pin. Active low logic output. This pin is driven low if an alert condition is detected and it is not masked by the corresponding bit

in the mask register. This pin has an internal configurable pull-up resistor.

PCAP1

AI/O

Noise Reduction Capacitor for DAC1, Optional.

NCAP1

AI/O

Noise Reduction Capacitor for DAC1, Optional.

VCM1

Common Mode Voltage for DAC1. Analog input/output.

IOUT1

AI/O

DAC1 Output Current.

RFB1_1

AI/O

Hardware Gain Selection for DAC1, Gain = 1.

RFB2 _1

AI/O

Hardware Gain Selection for DAC1, Gain = 2.

RFB4 _1

AI/O

Hardware Gain Selection for DAC1, Gain = 4.

AVDD

Analog Power Supply. 5 V ± 5%.

VREF

AI/O

Voltage Reference, 2.5 V. Input when using external reference, output or floating when using internal reference.

CVREF

AI/O

Decoupling Capacitor for Internal Reference, Optional.

AGND

Analog Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device.

RFB4 _0

AI/O

Hardware Gain Selection for DAC0, Gain = 4.

RFB2 _0

AI/O

Hardware Gain Selection for DAC0, Gain = 2.

RFB1 _0

AI/O

Hardware Gain Selection for DAC0, Gain = 1.

IOUT0

AI/O

DAC0 Output Current.

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