TMUX7348F datasheet(46/59 Pages) TI

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11 Power Supply Recommendations

The TMUX7348F and TMUX7349F operate across a wide supply range of ±5 V to ±22 V (8 V to 44 V in

single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the VDD

and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are ramped.

The fault supplies (VFP and VFN) provide the current required to operate the fault protection, and thus, must be

low impedance supplies. They can be derived from the primary supplies by using a resistor divider and buffer

or be an independent supply rail. The fault supplies must not exceed the primary supplies as it might cause

unexpected behavior of the switch. Use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the

VFP and VFN pins to ground for improved supply noise immunity.

The positive supply (VDD) must be ramped before the positive fault rail (VFP) for proper power sequencing of

the TMUX7348F and TMUX7349F. Similarly, the negative supply (VSS) must be ramped before the negative fault

voltage rail (VFN).

12 Layout

12.1 Layout Guidelines

The following images illustrate examples of a PCB layout with the TMUX7348F and TMUX7349F. Some key

considerations are:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and VSS to

GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as

possible. Make sure that the capacitor voltage rating is sufficient for the VDD and VSS supplies.

• Multiple decoupling capacitors can be used if their is a lot of noise in the system. For example, a 0.1-µF and

1-µF can be placed on the supply pins. If multiple capacitors are used, placing the lowest value capacitor

closest to the supply pin is recommended.

• Keep the input lines as short as possible.

• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

12.2 Layout Example

VDD

VSS

GND

TMUX7348F

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

VFN

VFP

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

Via to ground plane

Via to signal plane

Figure 12-1. TMUX7348FPW Layout Example

TMUX7348F

SCDS400 – MARCH 2022

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