LM5145 datasheet(21/69 Pages) TI

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An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 470-nF ceramic capacitor

to achieve a low-noise internal bias rail. Normally, VDDA is 5 V, but there are two operating conditions where it

regulates at 3.3 V. The first is in skip cycle mode when VOUT1 is set to 3.3 V and VOUT2 is disabled. The second

is in a cold-crank start-up where VIN is 3.8 V and VOUT1 is 3.3 V.

Internal power dissipation of the VCC regulator can be minimized by connecting VCCX to a 5-V output at VOUT1

or VOUT2 or to an external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC

and the internal VCC regulator is disabled. Tie VCCX to AGND if it is unused. Never connect VCCX to a voltage

greater than 6.5 V or less than –0.3 V. If an external supply is connected to VCCX to power the LM25143, VIN

must be greater than the external bias voltage during all conditions to avoid damage to the controller.

9.3.3 Enable (EN1, EN2)

The LM25143 contains two enable inputs. EN1 and EN2 facilitate independent start-up and shutdown control of

VOUT1 and VOUT2. The enable pins can be connected to a voltage as high as 70 V. If an enable input is greater

than 2 V, its respective output is enabled. If an enable pin is pulled below 0.4 V, the output is shut down. If both

outputs are disabled, the LM25143 is in a low-IQ shutdown mode with a 4-µA typical current drawn from VIN. TI

does not recommend leaving EN1 or EN2 floating.

9.3.4 Power-Good Monitor (PG1, PG2)

The LM25143 includes output voltage monitoring signals for VOUT1 and VOUT2 to simplify sequencing and

supervision. The power-good function can be used to enable circuits that are supplied by the corresponding

voltage rail or to turn on sequenced supplies. Each power-good output (PG1 and PG2) switches to a high

impedance open-drain state when the corresponding output voltage is in regulation. Each output switches low

when the corresponding output voltage drops below the lower power-good threshold (92% typical) or rises above

the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false tripping of the power-good

signals during transients. TI recommends pullup resistors of 100 kΩ from PG1 and PG2 to the relevant logic rail.

PG1 and PG2 are asserted low during soft start and when the corresponding buck regulator is disabled by EN1

or EN2.

If the LM25143 is in diode emulation mode (VDEMB = 0 V) and enters sleep mode, the power-good comparators

are turned off to reduce quiescent current consumption. When this occurs, PG1 and PG2 are open or pulled high

(if a pullup resistor is connected) such that output undervoltage or overvoltage events are not detected.

9.3.5 Switching Frequency (RT)

The LM25143 oscillator is programmed by a resistor between RT and AGND to set an oscillator frequency

between 100 kHz to 2.2 MHz. CLK1 is the clock for channel 1 and CLK2 is for channel 2. CLK1 and CLK2 are

180° out of phase. Use Equation 1 to calculate the RT resistance for a given switching frequency.

MHz

(1)

Under low VIN conditions when either of the on times of the high-side MOSFETs exceeds the programmed

oscillator period, the LM25143 extends the switching period of that channel until the PWM latch is reset by

the current sense ramp exceeding the controller compensation voltage. In such an event, the oscillators (CLK1

and CLK2) operate independently and asynchronously until both channels can maintain output regulation at the

programmed frequency.

The approximate input voltage level where this occurs is given by Equation 2.

IN(min)

OUT

OFF(min)

(2)

where

• tSW is the switching period.

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LM25143

SNVSC10 – MARCH 2022

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