LM5145 datasheet(6/69 Pages) TI

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Table 7-1. Pin Functions (continued)

I/O(1)

DESCRIPTION

NAME

NO.

EN1

An active high input (VEN1 > 2 V) enables output 1. If outputs 1 and 2 are disabled, the LM25143 is in

shutdown mode unless a SYNC signal is present at DEMB. EN1 must never be floating.

RES

Restart timer pin. An external capacitor configures the hiccup-mode current limiting. A capacitor at the

RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The

two regulator channels operate independently. One channel can operate in normal mode while the other

is in hiccup-mode overload protection. Hiccup mode commences when either channel experiences 512

consecutive PWM cycles with cycle-by-cycle current limiting. Connect RES to VDDA during power up to

disable hiccup-mode protection.

DEMB

Diode emulation pin. Connect DEMB to AGND to enable diode emulation mode. Connect DEMB to VDDA

to operate the LM25143 in forced PWM (FPWM) mode with continuous conduction at light loads. DEMB can

also be used as a synchronization input to synchronize the internal oscillator to an external clock.

MODE

Connect MODE to AGND or VDDA for dual-output or interleaved single-output operation, respectively.

This also configures the LM25143 with an EA transconductance of 1200 µS. Connecting a 10-kΩ resistor

between MODE and AGND sets the LM25143 for dual-output operation with an ultra-low IQ mode and an

EA transconductance of 60 µS.

AGND

Analog ground connection. Ground return for the internal voltage reference and analog circuits

VDDA

Internal analog bias regulator output. Connect a ceramic decoupling capacitor from VDDA to AGND.

Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz

and 2.2 MHz.

DITH

A capacitor connected between the DITH pin and AGND is charged and discharged with a 20-µA current

source. If dithering is enabled, the voltage on the DITH pin ramps up and down modulating the oscillator

frequency between –5% and +5% of the internal oscillator. Connecting DITH to VDDA during power up

disables the dither feature. DITH is ignored if an external synchronization clock is used.

SYNCOUT

SYNCOUT is a logic level signal with a rising edge approximately 90° lagging HO2 (or 90° leading HO1).

When the SYNCOUT signal is used to synchronize a second LM25143 controller, all phases are 90° out of

phase.

EN2

An active high input (VEN2 > 2 V) enables output 2. If outputs 1 and 2 are disabled, the LM25143 is in

shutdown mode unless a SYNC signal is present on DEMB. EN2 must never be floating.

(1)

P = Power, G = Ground, I = Input, O = Output

LM25143

SNVSC10 – MARCH 2022

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