AD9986 datasheet(35/37 Pages) AD

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Data Sheet

AD9986

THEORY OF OPERATION

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Rev. 0 | 35 of 37

The AD9986 is a highly integrated, mixed-signal, direct RF sam-

pling transceiver offering 4T2R and digital signal processing (DSP)

functions. The device delivers a versatile combination of high per-

formance, configurability, and low power consumption demanded by

wireless infrastructure applications, such as multiband macro 5G

and mm Wave 5G base station radios. The AD9986 offers support

for both time division duplex (TDD) and frequency division duplex

(FDD) modes of operation.

The receive path consists of two pipelined, 12-bit, 6 GSPS rate,

RF ADC cores. The transmit path consists of four 16-bit, 12 GSPS

maximum sample rate, RF DAC cores. Both the receive and trans-

mit paths are designed and optimized to sample and synthesize

signals up to 8 GHz, with maximum instantaneous bandwidths of up

to 1.2 GHz with a sample resolution of 16 bits. The device also sup-

ports lower resolutions such as 12 bits and 8 bits for applications

that do not require high dynamic range. The wide instantaneous

bandwidth allows the chip to support multiple carrier bands or a

single wide band within a single device. The combination of the

direct RF conversion architecture relaxes the requirements of the

RF filters when compared to traditional intermediate frequency (IF)

receivers. Several auxiliary functions, such as fast detect and signal

monitor, programmable FIR filter, transmit downstream power am-

plifier protection, and general-purpose input/output (GPIO) controls

are also integrated.

The DAC and ADC cores use sampling clocks that originate from

either an external clock source or an on-chip clock multiplier that

consists of an integer PLL circuit and voltage-controlled oscillator

(VCO).

The device features eight transmit and eight receive lanes that

support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B

standards in a single or dual link setup. Multichip synchronization

is supported via Subclass 1. The JESD204B/C interface supports

a wide range of setups depending on the interface bandwidth

requirements of the custom application specific IC (ASIC) or field-

programmable gate array (FPGA). Refer to the UG-1578 for more

information on device features and operation.

The AD9986 has an on-chip thermal management unit (TMU) that

can be used to measure die temperature as part of a thermal

management solution to guarantee thermal stability during system

operation. The device is controlled via a standard 4-wire serial

port interface (SPI) with support for 3-wire SPI communications. A

comprehensive set of power-down modes are included to minimize

power consumption during normal use. The AD9986 is packaged

in a 15 mm × 15 mm, thermally enhanced, 324-ball grid array

(BGA_ED).

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