AD8065 datasheet(32/60 Pages) AD

32 / 60 page

Data Sheet

AD3551R

THEORY OF OPERATION

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Rev. 0 | 32 of 60

The register map is divided in two regions, primary and secondary.

The registers related to interface configuration, DAC configuration,

and error flags are comprised in the primary region from Address

0x0 to Address 0x1E. If the QSPI pin is low, this region can only be

accessed in classic SPI mode with or without DDR, regardless of

the value of MULTI_IO_MODE in the TRANSFER_REGISTER.

The registers affecting the output value of the DAC are comprised

in the secondary region from Address 0x28 to Address 0x48. This

region can be accessed in any of the SPI modes, with or without

DDR.

If the QSPI pin is high, the interface is configured in full quad

SPI mode for any communication to primary or secondary region

registers.

Figure 85. Register Access Modes

SDIO Drive Strength

The driving strength of the SDIO lines on Pins 5, 6, 7 and

8 can be configured to four different levels by setting the

SDIO_DRIVE_STRENGTH bits in the INTERFACE_CONFIG_D

Higher drive strength value corresponds to a faster signal slew rate,

as shown in Figure 86. However, higher slew rate means higher

peak current and higher digital noise in the system. The default

value is medium low strength.

Figure 86. Driving Strength Options

DAC UPDATE MODES

There are several ways to update the DAC output, synchronously

or asynchronously, directly or indirectly.

A synchronous update occurs when the change of the DAC output

is triggered by an external signal, such as LDAC, which can be

common to many devices. In this case, the controller loads a value

in the input register that is later transferred to the DAC register

on the falling edge of the LDAC signal, causing the simultaneous

update of all VOUT signals.

To update the DAC using the LDAC signal, the

HW_LDAC_MASK_CH0 bit in the HW_LDAC_16B or

HW_LDAC_24B register, depending on the precision mode, must

be set to 0.

An asynchronous update occurs when the change of the DAC

output follows an operation on the register set. In this case, the

change is aligned with the SCLK edge that shifts the last register

bit in. The several combinations to update the DAC output are

described in Table 13.

Page mask registers are provided for compatibility with the multi-

channel devices, AD3552R and AD3542R. To update the DAC

using the page registers, the value of the SEL_CH0 bit in the

CH_SELECT_16B or CH_SELECT_24B register must be set to

1. Writing to the DAC_PAGE register transfers the data to the

CH0_DAC register and writing to the INPUT_PAGE register trans-

fers the data to the CH0_INPUT register. The data flow between

registers is summarized in Figure 87.

CHx_INPUT

CHx_DAC

INPUT_PAGE

DAC_PAGE

SEL_CHx

HW_LDAC_MASK_CHx

LDAC LOW

LDAC PULSED

Figure 87. DAC Data Flow Between Registers

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