PCF8545ATT datasheet(9/48 Pages) NXP

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PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

9 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

When display data is transmitted to the PCE85176AUG, the received display bytes are

stored in the display RAM in accordance with the selected LCD drive mode. The data is

stored as it arrives and depending on the current multiplex drive mode the bits are stored

singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a

7-segment display showing all drive modes is given in Figure 4; the RAM filling

organization depicted applies equally to other LCD types.

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address, but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.3.2)

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 3.

Display RAM bitmap

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