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PCF8545ATT датащи(PDF) 3 Page - NXP Semiconductors |
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PCF8545ATT датащи(HTML) 3 Page - NXP Semiconductors |
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3 / 48 page ![]() PCE85176AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1 — 12 January 2015 3 of 48 NXP Semiconductors PCE85176AUG 4 × 40 LCD segment driver for Chip-On-Glass 6. Pinning information 6.1 Pinning 6.2 Pin description Viewed from active side. For mechanical details, see Figure 27. Fig 2. Pinning diagram for PCE85176AUG (bare die) Table 4. Pin description Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol Pin Type Description SDA 1, 58, 59 input/output I2C-bus serial data line SCL 2, 3 input I2C-bus serial clock T1 4 input/output test pin; must be left open CLK 5 input/output clock line VDD 6 supply supply voltage OSC 7 input internal oscillator enable T2 to T4 8 to 10 input test pins; must be tied to VSS SA0 11 input I2C-bus address input VSS 12 supply ground supply voltage VLCD 13 supply LCD supply voltage BP0, BP2, BP1, BP3 14 to 17 output LCD backplane outputs S0 to S39 18 to 57 output LCD segment outputs |
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