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Data Sheet

AD7381-4

Rev. 0 | Page 19 of 31

RESOLUTION BOOST

The default resolution and output data size for the AD7381-4 is

14 bits. When the on-chip oversampling function is enabled the

performance of the ADC can exceed the default resolution. To

accommodate the performance boost achievable, it is possible

to enable an additional two bits of resolution. If the RES bit in

the Configuration 1 register is set to Logic 1 and the AD7381-4

is in a valid oversampling mode, the conversion result size for

the AD7381-4 is 16-bit. In this mode, 16 SCLK cycles are

required to propagate the data for the AD7381-4.

ALERT

The alert functionality is an out of range indicator and can be

used as an early indicator of an out of bounds conversion

result. An alert event triggers when the value in the conversion

result register exceeds the alert high limit value in the alert high

threshold register or falls below the alert low limit value in the

alert low threshold register. The alert high threshold register

and the alert low threshold register are common to all ADCs.

When setting the threshold limits, the alert high threshold must

always be greater than the alert low threshold. Detailed alert

information is accessible in the alert indication register.

The register contains two status bits per ADC, one corresponding

to the high limit, and the other to the low limit. A logical OR of

alert signals for all ADCs creates a common alert value. This

value can be configured to drive out on the ALERT function of

the SDOD/ALERT pin. The SDOD/ALERT pin is configured as

ALERT by configuring the following bits in the Configuration 1

•

Set the SDO bits to any value other than 0b00.

•

Set the ALERT_EN bit to 1.

•

Set a valid value in the alert high threshold register and the

alert low threshold register.

The alert indication function is available in oversampling

(rolling average, normal averaging, and in nonoversampling

modes).

The alert function of the SDOD/ALERT pin updates at the end

of conversion. The alert indication status bits in the ALERT

the next conversion.

Bits[7:0] in the alert indication register are cleared by reading

the alert indication register contents. The alert function of the

SDOD/ALERT pin is cleared with a falling edge of CS. Issuing a

software reset also clears the alert status in the alert indication

See Figure 8 for the ALERT timing diagram.

POWER MODES

The AD7381-4 has two power modes that can be set in the

Configuration 1 register: normal mode and shutdown mode.

These modes of operation provide flexible power management

options, allowing optimization of the power dissipation and

throughput rate ratio for different application requirements.

Program the PMODE bit in the Configuration 1 register to

configure the power modes in the AD7381-4. Set PMODE to

Logic 0 for normal mode and Logic 1 for shutdown mode.

Normal Mode

Keep the AD7381-4 in normal mode to achieve the fastest

throughput rate. All blocks within the AD7381-4 always remain

fully powered and an ADC conversion can be initiated by a

falling edge of CS when required. When the AD7381-4 is not

converting, it is in static mode and power consumption is

automatically reduced. Additional current is required to

perform a conversion. Therefore, power consumption of the

AD7381-4 scales with throughput.

Shutdown Mode

When slower throughput rates and lower power consumption

are required, use shutdown mode by either powering down the

ADC between each conversion or by performing a series of

conversions at a high throughput rate and then powering down

the ADC for a relatively long duration between these burst

conversions. When the AD7381-4 is in shutdown mode, all

analog circuitry powers down. The serial interface remains

active during shutdown mode to allow the AD7381-4 to exit

shutdown mode.

To enter shutdown mode, write to the power mode

configuration bit, PMODE, in the Configuration 1 register.

The AD7381-4 shuts down, and current consumption reduces.

To exit shutdown mode and return to normal mode, set the

PMODE bit in the Configuration 1 register to Logic 0. All

leaving shutdown mode. After exiting shutdown mode, allow

sufficient time for the circuitry to turn on before starting a

conversion.

SCLK

DB17

DB16

DB15

DB4

DB3

DB2

DB1

DB0

SDOA

SDOB

DB15

DB14

DB13

DB2

DB1

DB0

SDI

Figure 34. Resolution Boost

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