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Data Sheet

AD7381-4

Rev. 0 | Page 17 of 31

MODES OF OPERATION

The AD7381-4 has several on-chip configuration registers for

controlling the operational mode of the device.

OVERSAMPLING

Oversampling is a common method used in analog electronics

to improve the accuracy of the ADC result. Multiple samples of

the analog input are captured and averaged to reduce the noise

component from quantization noise and thermal noise (kTC

noise) of the ADC. The AD7381-4 offers an oversampling

function on-chip. The AD7381-4 has two user configurable

oversampling modes: normal averaging and rolling average.

The oversampling functionality is configured by programming

the OS_MODE bit and OSR bits in the Configuration 1

Normal Averaging Oversampling

Normal averaging oversampling mode can be used in

applications where slower output data rates are allowed and

where higher SNR or dynamic range is desirable. Normal

averaging involves taking a number of samples, adding them

together and dividing the result by the number of samples

taken. This result is then output from the device. The sample

data is cleared when the process completes.

Normal averaging oversampling mode is configured by setting

the OS_MODE bit to Logic 0 and having a valid nonzero value

in the OSR bits. Writing to the OSR bits has a two-cycle latency

before the register updates. That is, after writing to the OSR

bits, two conversion cycles take place before the conversion

results clock out with the updated OSR bits. The oversampling

ratio of the digital filter is controlled using the oversampling

bits, OSR (see Table 11). Table 11 provides the oversampling

bit decoding to select the different oversample rates. The output

result is decimated to 14-bit resolution. If required, additional

resolution can be achieved by configuring the resolution boost

bit (RES) in the Configuration 1 register. See the Resolution

Boost section for further details.

The number of samples (n), defined by the OSR bits, are taken

and added together, and the result is divided by n. The initial

ADC conversion is initiated by the falling edge of CS and the

AD7381-4 controls all subsequent samples in the oversampling

sequence internally. The sampling rate of the additional n

samples at the device maximum sampling rate is 4 MSPS. The

data is ready for readback on the next serial interface access.

After the averaging technique is applied, the sample data used

in the calculation is discarded. This process is repeated every

time the application needs a new conversion result and is

initiated by the next falling edge of CS.

As the output data rate is reduced by the oversampling ratio,

the serial peripheral interface (SPI) SCLK frequency required to

transmit the data is reduced accordingly.

Table 11. Normal Averaging Oversampling Overview

OSR, Bits[2:0]

OS Ratio

SNR (dB Typical)

2.5 V Internal Reference

3.3 V External Reference

Data Output Rate

(kSPS Maximum)

RES = 0

RES = 1

RES = 0

RES = 1

000

No OS

85.2

4000

001

88.2

1500

010

91.1

91.3

750

011

85.5

93.1

375

100

85.7

94.6

85.7

94.4

187.5

101

85.9

95.6

85.8

95.5

93.75

110

Invalid

Not applicable

111

Invalid

Not applicable

ACQ

INTERNAL

DON'T CARE

t0 RESULT

SDOA

DON'T CARE

t0 RESULT

SDOB

CONVERT START AT

Figure 32. Normal Averaging Oversampling Operation

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