LT8331 datasheet(9/30 Pages) AD

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LT8365

Rev. A

For more information www.analog.com

OPERATION

The LT8365 uses a fixed frequency, current mode control

scheme to provide excellent line and load regulation. Op-

eration can be best understood by referring to the Block

Diagram. An oscillator (with frequency programmed by a

resistor at the RT pin) turns on the internal power switch at

the beginning of each clock cycle. Current in the inductor

then increases until the current comparator trips and turns

off the power switch. The peak inductor current at which

the switch turns off is controlled by the voltage on the VC

pin. The error amplifier servos the VCpinbycomparingthe

voltage on the FBX pin with an internal reference voltage

(1.60V or –0.80V, depending on the chosen topology).

When the load current increases it causes a reduction in

the FBX pin voltage relative to the internal reference. This

causes the error amplifier to increase the VC pin voltage

until the new load current is satisfied. In this manner, the

error amplifier sets the correct peak switch current level

to keep the output in regulation.

The LT8365 is capable of generating either a positive or

negative output voltage with a single FBX pin. It can be

configured as a boost or SEPIC converter to generate a

positive output voltage, or as an inverting converter to

generate a negative output voltage. When configured as

a Boost converter, as shown in the Block Diagram, the

FBX pin is pulled up to the internal bias voltage of 1.60V

by a voltage divider (R1 and R2) connected from VOUT

to GND. Amplifier A2 becomes inactive and amplifier A1

performs (inverting) amplification from FBX to VC. When

the LT8365 is in an inverting configuration, the FBX pin

is pulled down to –0.80V by a voltage divider from VOUT

to GND. Amplifier A1 becomes inactive and amplifier A2

performs (non-inverting) amplification from FBX to VC.

If the EN/UVLO pin voltage is below 1.6V, the LT8365

enters undervoltage lockout (UVLO), and stops switching.

When the EN/UVLO pin voltage is above 1.68V (typical),

theLT8365resumesswitching.IftheEN/UVLOpinvoltage

is below 0.2V, the LT8365 draws less than 1µA from VIN.

For the SYNC/MODE pin tied to ground or <0.14V, the

LT8365 will enter low output ripple Burst Mode opera-

tion for ultra low quiescent current during light loads to

maintain high efficiency. For a 100k resistor from SYNC/

MODE pin to GND, the LT8365 uses Burst Mode opera-

tion for improved efficiency at light loads but seamlessly

transitions to Spread-Spectrum Modulation of switching

frequency for low EMI at heavy loads. For the SYNC/

MODE pin floating (left open), the LT8365 uses pulse-

skipping mode, at the expense of hundreds of microamps,

to maintain output voltage regulation at light loads by

skipping switch pulses. For the SYNC/MODE pin tied to

INTVCC or >1.7V, the LT8365 uses pulse-skipping mode

and performs Spread-Spectrum Modulation of switching

frequency. For the SYNC/MODE pin driven by an external

clock, the converter switching frequency is synchronized

to that clock and pulse-skipping mode is also enabled. See

the Pin Functions section for SYNC/MODE pin.

The LT8365 includes a BIAS pin to improve efficiency

acrossallloads.TheLT8365intelligentlychoosesbetween

the VIN and BIAS pins to supply the INTVCC for best ef-

ficiency. The INTVCC supply current can be drawn from

the BIAS pin instead of the VIN pin for 4.4V ≤ BIAS ≤ VIN.

Protection features ensure the immediate disable of

switching and reset of the SS pin for any of the following

faults: internal reference UVLO, INTVCC UVLO, switch cur-

rent > 1.5× maximum limit, EN/UVLO < 1.6V or junction

temperature > 170°C.

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