LTC4155 datasheet(21/26 Pages) AD

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LTC4041

Rev A

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APPLICATIONS INFORMATION

Supercapacitor Charger Stability Considerations

The LTC4041’s switching supercapacitor charger contains

three control loops: constant-voltage, constant-current,

and input current limit loop, all of which are internally

compensated. However, various external variables like

load and component values may interfere with the inter-

nal compensation and cause instability.

In constant-current mode, the PROG pin is in the feedback

loop rather than the SCAP pin. Because of the additional

pole created by any PROG pin capacitance, capacitance on

this pin must be kept to a minimum. For the constant-cur-

rent loop to be stable, the pole frequency at the PROG pin

should be kept above 1MHz. Therefore, if the PROG pin

has a parasitic capacitance, CPROG, the following equa-

tion should be used to calculate the maximum resistance

value for RPROG:

RPROG ≤

2π • 1MHz • CPROG

Alternatively, for RPROG = 4k (500mA setting), the maxi-

mum allowable capacitance on the PROG pin is 40pF. If

any measuring device is attached to the PROG pin for

monitoring the charge current, a 1M isolation resistor

should be inserted between the PROG pin and the device.

Backup Boost Stability Considerations

The LTC4041’s backup boost converter is internally com-

pensated. However, system capacitance less than 100µF

or over 1000μF will adversely affect the phase margin and

hence the stability of the converter. Also, if the right-half-

plane (RHP) zero moves down in frequency due to exter-

nal load conditions or the choice of the inductor value,

the phase margin may be reduced to a point which causes

instability. If the output power is POUT, inductor value is

L, efficiency is η, and the input to the boost converter

is VSCAP, the RHP zero frequency can be expressed as

follows:

fRHP =

VSCAP

(

)

2 • π • L • POUT

• η

For the LTC4041’s backup boost to be able to supply

12.5W of output power (2.5A at 5V) from a stack of

supercapacitors charged to 3.2V, the maximum inductor

size should not exceed 2.2μH because of the RHP zero

consideration. Also, too much resistance between the

supercapacitor and the SCAP pin can lower the effective

input voltage of the boost converter causing the RHP zero

to shift lower in frequency and thus causing instability.

This is why it is important to minimize the lead resistance

and place the supercapacitor as close to the SCAP pin as

possible.

PCB Layout Considerations

Since the LTC4041 includes a high-current high-frequency

switching converter, the following guidelines should be

followed in the printed circuit board (PCB) layout in order

to achieve optimum performance and minimum electro-

magnetic interference (EMI).

1. Even though the converter can operate in both step-

down (buck) and step-up (boost) mode, there is only

one hot-loop containing high-frequency switching

currents. The simplified diagram in Figure 3 can be

used to explain the hot-loop in the LTC4041 switch-

ing converter. Current follows the blue loop when the

switch S2 (NMOS) is closed and the red loop when

switch S1 (PMOS) is closed. So it is evident that the

current in the CSCAP capacitor is continuous whereas

the CSYS current is discontinuous forming a hot loop

with the VSYS pins and GND as indicated by the green

loop. Since the amount of EMI is directly proportional

to the area of this loop, the VSYS capacitor, prioritized

over all else, should be placed as close to the VSYS

pins as possible and the ground side of the capacitor

should return to the ground plane through an array

of vias.

Figure 3. Hot-Loop Illustration for

the LTC4041 Switching Converter

VSCAP

HOT LOOP

CSCAP

4041 F03

CSYS

VSYS

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