LTC4155 datasheet(13/26 Pages) AD

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LTC4041

Rev A

For more information www.analog.com

Figure 1 shows the buck charger operating in discon-

tinuous mode. The supercapacitor voltage is at 0V and

the charge current is programmed to 500mA. The VSYS

voltage ripple, which is also shown in the same figure, is

about 14mV in this example.

Figure 1. Charge Current Waveform for VSCAP <1V

OPERATION

Charge Termination

The charge voltage of the supercapacitor (or the stack) is

set by an external resistor divider connected between the

SCAP pin and ground with its midpoint connected to the

CAPFB pin. As the voltage on the supercapacitor reaches

the pre-set charge voltage, the constant-voltage (CV) loop

of the buck charger starts to regulate the supercapacitor

voltage and the charge current decreases naturally. Once

the charge current drops to 12.5% of the programmed

charge current, the buck charger is disabled and no

charge current will be delivered to the supercapacitor. To

enable the buck charger and resume charging, the super-

capacitor voltage has to fall below the automatic recharge

threshold.

Automatic Recharge

Once the supercapacitor charger terminates, it remains

off drawing only microamperes of current from the super-

capacitor. To ensure that the supercapacitor is always

topped off, a charge cycle automatically begins when

the supercapacitor voltage falls below VRECHRG (typically

97.5%). To prevent brief excursions below VRECHRG from

enabling/disabling the buck charger unnecessarily, the

supercapacitor voltage must be below VRECHRG for at least

5ms (typical) for the charger to be re-enabled.

Supercapacitor Charge Status Indication via the

CAPGD Pin

The CAPGD pin is an open-drain output used to indicate

that the supercapacitor (or the stack) voltage has reached

92.5% of its regulation point. The CAPGD pin is pulled

low until the supercapacitor voltage is above 92.5% of

the final charge voltage at which point the CAPGD pin

becomes high impedance. The supercapacitor voltage has

to fall below 90% of the regulation point to pull the CAPGD

pin low again. The CAPGD pin requires an external pull-up

resistor to either the VSYS pin or to another appropriate

power source. When the charger is disabled, the CAPGD

pin is pulled low.

Supercapacitor Balancer

The LTC4041 has an internal balancer that servos the mid-

point of a stack of two supercapacitors, i.e. the BAL pin

voltage, to half the stack voltage (VSCAP). To activate the

balancer, tie the CAPSEL pin high to indicate that a stack

of two supercapacitors is connected to the SCAP pin with

the midpoint of the stack connected to the BAL pin. The

source/sink capability of the internal balancer is typically

±50mA with VSCAP at 5V. The balancer will try to balance

the stack of supercapacitors even after charging is com-

pleted. The balancer circuitry is disabled if the charger is

disabled. The balancer is also disabled if the CAPSEL pin

is low. When a single supercapacitor is connected to the

SCAP pin, tie the CAPSEL pin low and float the BAL pin.

Differential Undervoltage Lockout

An undervoltage lockout circuit monitors the differential

voltage between VSYS and SCAP and shuts off the char-

ger if the SCAP voltage reaches within 50mV of the VSYS

voltage. Charging does not resume until this difference

increases to 150mV.

CSYS = 100µF

12µs/DIV

VSYS

20mV/DIV

ISCAP

500mA/DIV

AC–COUPLED

4041 F01

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