поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

ADRF5473BCZ-GP датащи(PDF) 15 Page - Analog Devices

номер детали ADRF5473BCZ-GP
подробное описание детали  Die on Carrier, Silicon Digital Attenuator, 0.5 dB LSB, 6-Bit, 100 MHz to 40 GHz
PDF  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADRF5473BCZ-GP датащи(HTML) 15 Page - Analog Devices

Back Button ADRF5473BCZ-GP Datasheet HTML 9Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 10Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 11Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 12Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 13Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 14Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 15Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 16Page - Analog Devices ADRF5473BCZ-GP Datasheet HTML 17Page - Analog Devices  
Zoom Inzoom in Zoom Outzoom out
 15 / 17 page
background image
Data Sheet
ADRF5473
THEORY OF OPERATION
analog.com
Rev. 0 | 15 of 17
PARALLEL MODE INTERFACE
The ADRF5473 has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 7. The parallel control interface is activated when
PS is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
To enable direct parallel mode, the LE pad must be kept high. The
attenuation state is changed by the control voltage inputs (D0 to
D5) directly. This mode is ideal for manual control of the attenuator.
Latched Parallel Mode
To enable latched parallel mode, keep the LE pad low when
changing the control voltage inputs (D0 to D5) to set the attenuation
state. When the desired state is set, toggle LE high to transfer
the 6-bit data to the bypass switches of the attenuator array, and
then toggle LE low to latch the change into the device until the
next desired attenuation change (see Figure 27 and Table 2 for
additional information).
Figure 27. Latched Parallel Mode Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com