Data Sheet

ADRF5473

THEORY OF OPERATION

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Rev. 0 | 14 of 17

SERIAL OR PARALLEL MODE SELECTION

The ADRF5473 can be controlled in either serial or parallel mode

by setting the PS pad to high or low, respectively (see Table 8).

Table 8. Mode Selection

PS

Control Mode

Low

Parallel

High

Serial

SERIAL MODE INTERFACE

The ADRF5473 supports a 4-wire SPI: serial data input (SERIN),

clock (CLK), serial data output (SEROUT), and latch enable (LE).

The serial control interface is activated when PS is set to high.

The ADRF5473 attenuation states can be controlled using 6-bit or

8-bit SERIN data. If an 8-bit word is used to control the state of

the attenuator, the first two bits, D7 and D6, are don’t care bits. It

does not matter if these two bits are held low or high, or if they are

omitted altogether. Only Bits[D0:D5] set the state of the attenuator.

In serial mode, the SERIN data is clocked MSB first on the rising

CLK edges into the shift register. Then, LE must be toggled high

to latch the new attenuation state into the device. LE must be set

to low to clock new SERIN data into the shift register as CLK is

masked to prevent the attenuator value from changing if LE is kept

high. See Figure 25, Table 2, and Table 7 for additional information.

Using SEROUT

The ADRF5473 also features a serial data output (SEROUT).

control a cascaded attenuator using a single SPI bus.

Figure 26 shows the serial out timing diagram.

When using the attenuator in a daisy-chain operation, 8-bit SERIN

data must be used due to the eight clock cycle delay between

SERIN and SEROUT. The SEROUT pad does not support high

impedance mode. A tristate buffer can be used to interface a

shared bus.

Figure 25. Serial Control Timing Diagram

Figure 26. Serial Output Timing Diagram