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High Speed CMOS Logic – 74HC240

Rev 1.1

30/11/21

5. ot production tested in die form, characterized by chip design.

N

Figure 1 – Propagation Delay - Input 1A or 2A to Output 1Y or 2Y

Switching Waveforms

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

80

100

100

4.5V

16

20

20

Maximum Propagation

Delay, Input A to

Output Y (Figure 1)

6.0V

Input

14

17

17

ns

2.0V

110

140

140

4.5V

22

28

28

Maximum Propagation

Delay, OE to Output Y

(Figure 2, 3)

6.0V

Input

19

24

24

ns

2.0V

110

140

140

4.5V

22

28

28

Maximum Propagation

Delay, OE to Output Y

(Figure 2, 3)

6.0V

Input

19

24

24

ns

2.0V

60

75

75

4.5V

12

15

15

Maximum Output Rise

and Fall Time, Any

Output

(Figure 1)

6.0V

Input

10

13

13

ns

Maximum Input

Capacitance

-

-

10

10

10

pF

Maximum 3-State

Ouput Input (High-Z)

-

-

15

15

15

pF

TYPICAL

Power Dissipation

Capacitance

6

-

32

pF