W7100A datasheet(21/160 Pages) WIZNET

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W7100A Datasheet v1.2.5

P2.7

Port2 input/output, Ext Memory Addr15

P3.0

Port3 input/output, Ext Memory Addr16

P3.1

Port3 input/output, Ext Memory Addr17

P3.2

Port3 input/output, Ext Memory Addr18

P3.3

Port3 input/output, Ext Memory Addr19

P3.4

Port3 input/output, Ext Memory Addr20

P3.5

Port3 input/output, Ext Memory Addr21

P3.6

Port3 input/output, Ext Memory Addr22

P3.7

Port3 input/output, Ext Memory Addr23

Note: User can control the GPIO I/O driving voltage using PxPU/PxPD SFR.

Note: In that case, GPIO0~3 is used to transfer External memory address and data. Please

refer to the ‘2.3 External Data Memory Access’

1.4.2.7 External Memory Interface

Pin name

Num

I/O Type

Description

ALE

Data memory address bus [7:0] latch enable

nWR

External data memory write

nRD

External data memory read

Note: When user using External memory by standard 8051 interface, P0[7:0] can transfer

Data[7:0] or Address[7:0] by ALE pin control.

1.4.2.8 Media Interface

Pin name

Pin number

I/O

Pu/Pd

Description

100pin

64pin

TXON

TXON/TXOP Signal Pair, The differential data is

transmitted to the media on the TXON/TXOP

signal pair

TXOP

RXIN

RXIN/RXIP Signal Pair, The differential data from

the media is received on the RXIN/RXIP Signal

pair

RXIP

RESETBG

PHY Off-chip resistor, Connect a resistor of 12.3

㏀

±1% to the ground. Refer to the “Reference

schematic”

For the best performance,

1. Make the length of RXIP / RXIN signal pair (RX) same if possible.

2. Make the length of TXOP / TXON signal pair (TX) same if possible.

3. Locate the RXIP and RXIN signal as near as possible.

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