W7100A datasheet(68/160 Pages) WIZNET

номер детали	W7100A

подробное описание детали	Release with W7100 launching

PDF	160 Pages

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W7100A Datasheet v1.2.5

Watchdog Timer

7.1

Overview

The Watchdog Timer is driven by the main system clock that is supplied by a series of dividers

as shown in the Figure below. The divider output is selectable and determines the timeout

intervals. When the timeout is reached, an interrupt flag will be set, and if enabled, a reset

will be occurred. When interrupt enable bit and global interrupt are enabled, the interrupt

flag will activate the interrupts. The reset and interrupt are completely discrete functions

that may be acknowledged separately, together or even ignored depending on the application.

Figure 7.1 Watchdog Timer Structure

7.2

Interrupts

Watchdog interrupt related bits are shown below. An interrupt can be turned on/off by the

IE (0xA8) and EIE (0xE8) registers, and high/low priorities can be set in the EIP EIP (0xF8)

IE (0xA8)

Reset

ET2

ET1

EX1

ET0

EX0

0x00

Figure 7.2 Interrupt Enable Register

EIE (0xE8)

Reset

EWDI

EINT5

EINT4

EINT3

EINT2

0x00

Figure 7.3 Extended Interrupt Enable Register

Note: EA - Enable global interrupt

EWDI - Enable Watchdog interrupt

W7100A датащи(PDF) 68 Page - WIZnet Co., Ltd