EDB8164B4PR-1DATF-R datasheet(58/152 Pages) MICRON

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Figure 35: Write Data Mask – Second Data Bit Masked

DQS_c

CK_c

Don’t Care

CMD

WL = 2

tDQSSmax

tDQSSmin

IN0

IN2

IN3

WRITE

tWTR

tWR

IN0

IN2

IN3

Case 1: tDQSSmin

Case 2: tDQSSmax

IN1

CK_t

DQS_t

DQS_c

DQS_t

Note:

1. For the data mask function, WL = 2, BL = 4 is shown; the second data bit is masked.

PRECHARGE Command

The PRECHARGE command is used to precharge or close a bank that has been activa-

ted. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH,

CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command

can be used to precharge each bank independently or all banks simultaneously. For a 4-

bank device, the AB flag and bank address bits BA0 and BA1 are used to determine

which bank(s) to precharge. For an 8-bank device, the AB flag and the bank address bits

BA0, BA1, and BA2 are used to determine which bank(s) to precharge. The precharged

bank(s) will be available for subsequent row access tRPab after an all bank PRECHARGE

command is issued, or tRPpb after a single-bank PRECHARGE command is issued.

To ensure that an 8-bank device can meet the instantaneous current demand required

to operate, the row precharge time (tRP) for an all bank PRECHARGE in an 8-bank de-

vice (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE

(tRPpb). For a 4-bank device, tRPab is equal to tRPpb.

ACTIVATE to PRECHARGE timing is shown in ACTIVATE Command.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

PRECHARGE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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