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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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EDB8164B4PR-1DATF-R датащи(PDF) 57 Page - Micron Technology |
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EDB8164B4PR-1DATF-R датащи(HTML) 57 Page - Micron Technology |
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57 / 152 page  Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16 Bank n col addr a Col addr a READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ RL = 3 Transitioning data BST prohibited NOP NOP BST NOP RL × tCK + tDQSCK + tDQSQ NOP D OUT A4 D OUT A5 D OUT A6 D OUT A7 D OUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP Notes: 1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after the rising edge of the clock where the BST command is issued. 2. BST can only be issued an even number of clock cycles after the READ command. 3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command. Write Data Mask On the LPDDR2 device, one write data mask (DM) pin for each data byte (DQ) is sup- ported, consistent with the implementation on LPDDR SDRAM. Each DM can mask its respective DQ for any given cycle of the burst. Data mask timings match data bit timing, but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched system timing. Figure 34: Data Mask Timing DQS_c DQS_t DQ DM tDS tDH tDS V IL(AC) V IH(AC) V IL(AC) V IH(AC) V IL(DC) V IH(DC) tDH V IL(DC) V IH(DC) Don’t Care 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Write Data Mask 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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